Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 2 Eike Schweißguth, Arne Wall Institute MD, University of Rostock

Agenda • Multiplier • Adder • Pipelining • Metric • Frequency Response

Multiplier – Modification of the Coefficients • reduced size of coefficients from 16 bits to 10 bits (deleted lower 6 bits)  less area on chip; more speed due to shorter adders • Booth encoded coefficients lead to a maximum of 3 partial products • use of hard wired multipliers

Multiplier – Structure of the Multiplier Partial Products Adder Register Adder Register Previous Coefficient Register Adder

Adder • optimized carry path on Virtex 6 FPGA  fast Ripple Carry Adder • use of Ripple Carry Adder instead of Carry Increment Adder • consideration to use Carry Increment Adder on the ASIC • easy exchange of adders possible in VHDL-Code

Pipelining • implemented Direct Form II of the FIR-filter • 2 additional pipeline stages between the adders of the multiplier • maximum of one adder in one pipeline stage • too many register stages require more area and let the metric decrease 3pipeline stages used in the design

Pipelining • the expected increase in frequency can be confirmed

Metric after Synthesis

Metric after Place & Route

Metric of first Design

Frequency Response Low Influence of modified Coefficients

Thank you for your attention!

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design