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Chien-Mo Li 李建模 cmli@cc.ee.ntu.edu.tw http://cc.ee.ntu.edu.tw/~cmli. 作專題 得大獎!. 2006 CAD 競賽特優 : 林修霆 吳濟安. 真的嗎!?作專題還可以出國. 獲得優等以上隊伍之指導老師與參賽學生得以全額補助 ( 每人七萬元 ) 出國參與國際性研討會. 2005 DAC, Anaheim. 2006 DAC, San Francisco. Software Project Topics (1). 今年 CAD 競賽題目(定題組) : IC 內建自測 可以兩三人合作 五月截止
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Chien-MoLi 李建模cmli@cc.ee.ntu.edu.twhttp://cc.ee.ntu.edu.tw/~cmli
作專題 得大獎! • 2006 CAD 競賽特優 : 林修霆 吳濟安
真的嗎!?作專題還可以出國 • 獲得優等以上隊伍之指導老師與參賽學生得以全額補助 ( 每人七萬元 ) 出國參與國際性研討會 2005 DAC, Anaheim 2006 DAC, San Francisco
Software Project Topics (1) • 今年CAD競賽題目(定題組):IC內建自測 • 可以兩三人合作 • 五月截止 • 研究題目,實作,修正改進 • 已有部分參考原始碼 • 雖然比較辛苦,但是成果亦十分豐碩 • 歡迎愛好挑戰者,愛好思考者,努力不懈,想得大獎者,想出國者.....
Software Project Topics (2) • CAD競賽不定題組 • 低功率自動測試向量產生 • Low Power Automatic Test Pattern Generator • 可以兩三人合作 • 已有原始碼 • 工作:研究原始碼,加上GUI介面,修正改進 • 與去年特優得主合作 • 贏面大增!
Software Project Topics (3) • 錯誤模擬軟體(Fault Simulator) • 此軟體為測試之重要工具。目前學術界公開paper演算法 • 目標將之實做(C,C++) • 與paper 數字比較 • 將演算法改進 • 你將學到 • EDA演算法等技巧
Hardware Project Topic (1) • 記憶體自我測試(BIST)實作及驗證 • 修改既有VERILOG程式碼,燒錄在FPGA板 • 自我測試介面程式 • 用儀器測試驗證 • 可2-3人合作 • 你將學到VERILOG,FPGA實作及測試驗證等技巧
Will Testing Eventually More Expensive Than Silicon? Source: National Technology Roadmap for Semiconductor ’97 Semiconductor Industry Association, USA
What is Testing? • The process of determining whether a piece of equipment • Is functioning correctly, or • Is defective
Testing Important in All Stages design Verification Debug Fabrication feedback Silicon Debug Mass production Good chips Test customers Some failing chips Returned Diagnosis faults Failure analysis Defects & their causes Feedback to design, test & fab.
Digital Logic Testing Example • Faulty AND gate • Defect: unwanted wires (short to ground) • Fault: b stuck at logic 0 • b always stuck at logic 0 • How to test this fault? • Apply test pattern a=b=1 • Good response =1, faulty response =0 a f b
Why Research in Testing? • Testing can help you to • Enhance Profit • Reduce test cost • Guarantee IC quality • Made In Taiwan = high quality • Shorten Time to Market • Verification, Debug, Diagnosis
My Projects • 國科會 TFT flexible electronics design and testing • 國科會 Self Testable, Low power digital spread spectrum transceiver • 經濟部 IP Library • IP design methodology • Focus on testing and Verification
Requirements for Students • Most IMPORTANTLY • Self motivated, willing to learn • Second (topic dependent) • Switching ckt. and logic design • Computer Programming
What to Learn More about Testing? • My office • EE building II, room 339 • My lab • BL- 427 • Email • cmli@cc.ee.ntu.edu.tw • Personal Homepage • http://cc.ee.ntu.edu.tw/~cmli/ • VLSI and SOC Testing class • Linked from my homepage
Introduction to EDA • Newly offered 系定選修 • Prof. Chen SJ, Li CM • Monday 9:10 am – 12:20pm (EE-II 146) • Outline • VLSI design introduction • Graph theory and complexity • Physical design • Simulation • Synthesis and verification • Testing • 4 HW, Midterm, Final, 2 program assignments