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CPE 528: Session #9

CPE 528: Session #9. Department of Electrical and Computer Engineering University of Alabama in Huntsville. Outline. Review: VHDL Packages for Synthesis Review: VHDL for Combinational Logic Synthesis VHDL for Sequential Logic Synthesis VHDL for RTL Level Synthesis Structural VHDL

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CPE 528: Session #9

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  1. CPE 528: Session #9 Department of Electrical and Computer Engineering University of Alabama in Huntsville

  2. Outline • Review: VHDL Packages for Synthesis • Review: VHDL for Combinational Logic Synthesis • VHDL for Sequential Logic Synthesis • VHDL for RTL Level Synthesis • Structural VHDL • Implementation Technology Considerations • Summary

  3. VHDL Packages for SynthesisBase Types • Standard bit types may be used • Typically IEEE 1164 Std. types are used • std_ulogic type • Values ‘U’, ‘X’, ‘W’, and ‘-’ are called metalogical values for synthesis USE IEEE.std_logic_1164.ALL; TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); • std_logic type - resolved std_ulogic type

  4. VHDL Packages for SynthesisBase Types (cont.) • The std_logic_1164 package also contains: • Vectors of std_ulogic and std_logic • Subtypes of std_logic - X01, X01Z, UX01, UX10Z • Logic functions with various arguments - std_ulogic, std_logic, std_logic_vector FUNCTION “and” (l,r : std_ulogic;) RETURN UX01; FUNCTION “nand” (l,r : std_ulogic;) RETURN UX01; FUNCTION “or” (l,r : std_ulogic;) RETURN UX01; FUNCTION “nor” (l,r : std_ulogic;) RETURN UX01; FUNCTION “xor” (l,r : std_ulogic;) RETURN UX01; FUNCTION “xnor” (l,r : std_ulogic;) return ux01; FUNCTION "not" (l,r : std_ulogic) RETURN UX01; • Conversion functions FUNCTION To_bit(s:std_ulogic) RETURN bit; FUNCTION To_bitvector(s:std_ulogic_vector) RETURN bit_vector; FUNCTION To_StdULogic(b:bit) RETURN std_ulogic;

  5. VHDL Packages for SynthesisBase Types (cont.) • Unknown functions • Clock edge functions FUNCTION rising_edge (SIGNAL s:std_ulogic) RETURN boolean; FUNCTION falling_edge (SIGNAL s:std_ulogic) RETURN boolean; FUNCTION Is_X (s:std_ulogic_vector) RETURN boolean; FUNCTION Is_X (s:std_logic_vector) RETURN boolean; FUNCTION Is_X (s:std_ulogic) RETURN boolean;

  6. VHDL Packages for SynthesisArithmetic Packages • All synthesis tools support some type of arithmetic packages • Synopsis developed packages based on std_logic_1164 package - supported by many other synthesis tools • std_logic_arith • std_logic_signed • std_logic_unsigned • Actel synthesis tools support their own package • asyl.arith • IEEE has developed standard packages for synthesis IEEE Std. 1076.3 • Numeric_Bit • Numeric_Std UAH-CPE528

  7. IEEE Std 1076.3 PackagesNumeric_Bit • Type declarations for signed and unsigned numbers USE IEEE.numeric_bit.ALL; TYPE unsigned IS ARRAY (natural RANGE <> ) OF bit; TYPE signed IS ARRAY (natural RANGE <> ) OF bit; • Arithmetic operators - various combinations of signed and unsigned arguments FUNCTION “abs” (arg:unsigned) RETURN unsigned; FUNCTION “-” (arg:unsigned) RETURN unsigned; FUNCTION “+” (l,r:unsigned) RETURN unsigned; FUNCTION “-” (l,r:unsigned) RETURN unsigned; FUNCTION “*” (l,r:unsigned) RETURN unsigned; FUNCTION “/” (l,r:unsigned) RETURN unsigned; FUNCTION “rem” (l,r:unsigned) RETURN unsigned; FUNCTION “mod” (l,r:unsigned) RETURN unsigned; UAH-CPE528

  8. IEEE Std 1076.3 PackagesNumeric_Bit • Comparison operators - various combinations of signed and unsigned arguments FUNCTION “>” (l,r:unsigned) RETURN boolean; FUNCTION “<” (l,r:unsigned) RETURN boolean; FUNCTION “<=” (l,r:unsigned) RETURN boolean; FUNCTION “>=” (l,r:unsigned) RETURN boolean; FUNCTION “=” (l,r:unsigned) RETURN boolean; FUNCTION “/=” (l,r:unsigned) RETURN boolean; • Shift and rotate functions FUNCTION shift_left (arg:unsigned; count:natural) RETURN unsigned; FUNCTION shift_right (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rotate_left (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rotate_right (arg:unsigned; count:natural) RETURN unsigned; FUNCTION sll (arg:unsigned; count:natural) RETURN unsigned; FUNCTION slr (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rol (arg:unsigned; count:natural) RETURN unsigned; FUNCTION ror (arg:unsigned; count:natural) RETURN unsigned; UAH-CPE528

  9. IEEE Std 1076.3 PackagesNumeric_Bit • Resize functions FUNCTION resize (arg:unsigned;new_size:natural) RETURN unsigned; FUNCTION resize (arg:signed;new_size:natural) RETURN signed; • Conversion functions FUNCTION to_integer (arg:unsigned) RETURN natural; FUNCTION to_unsigned (arg,size:natural) RETURN unsigned; • Logical operators FUNCTION “not” (l:unsigned) RETURN unsigned; FUNCTION “and” (l,r:unsigned) RETURN unsigned; FUNCTION “or” (l,r:unsigned) RETURN unsigned; FUNCTION “nand” (l,r:unsigned) RETURN unsigned; FUNCTION “nor” (l,r:unsigned) RETURN unsigned; FUNCTION “xnor” (l,r:unsigned) RETURN unsigned; • Edge detection functions FUNCTION rising_edge(SIGNAL s:bit) RETURN boolean; FUNCTION falling_edge(SIGNAL s:bit) RETURN boolean; UAH-CPE528

  10. IEEE Std 1076.3 PackagesNumeric_Std • Similar to Numeric_Bit package using std_logic_1164 types • Signed and unsigned type declarations • Aritmetic operators • Comparison operators • Shift and rotate functions • Resize functions • Conversion functions • Logical operators • Match functions USE IEEE.numeric_std.ALL; FUNCTION std_match (l,r:std_ulogic) RETURN boolean; FUNCTION std_match (l,r:unsigned) RETURN boolean; • Translation functions FUNCTION to_01 (s:unsigned; xmap:std_logic := ‘0’) RETURN unsigned; UAH-CPE528

  11. Outline • VHDL Packages for Synthesis • VHDL for Combinational Logic Synthesis • Types • Attributes • Concurrent signal assignment statements • Operators • Processes • If statements • Case statements • Loops • Procedures and functions • Tri state logic • Use of don’t cares • After clauses • Inferring latches • Problems to avoid • VHDL for Sequential Logic Synthesis • VHDL for RTL Level Synthesis

  12. Types • Scalar types • Enumeration types are supported • Bit, Boolean, and Std_Ulogic map to single bits • Mapping of other types will be made by the tool unless the ENUM_ENCODING attribute is used • Character type is suppored • Severity_level type is ignored • Integer type, Natural, and Positive are supported • A subtype with a descrete range should be used or the default 32 bit length will be synthesized • Physical types (e.g., time) are ignored • Floating point type is ignored - references to floating point objects can occur only within ignored constructs, e.g., After clauses, etc. UAH-CPE528

  13. Types (cont.) • Array types are supported • Bounds must be specified directly or indirectly as static values of an integer type • Element subtype must denote a scalar type or a one dimensional vector of an enumerated type that denotes single bits TYPE integer_array IS ARRAY(natural RANGE 7 DOWNTO 0) OF integer; TYPE boolean_array IS ARRAY(integer RANGE <>) OF boolean; ... SIGNAL bool_sig : boolean_array(-1 to 1); • Record types are supported • Access types are ignored • File types are ignored • File objects and file operations are not supported UAH-CPE528

  14. Attributes • The following predefined attributes for types are supported: • t’BASE • t’LEFT • t’RIGHT • t’HIGH • t’LOW • The following predefined attributes for array objects are supported: • a’LEFT • a’RIGHT • a’HIGH • a’LOW • a’RANGE • a’REVERSE_RANGE • a’LENGTH • The following predefined attributes for signals are supported • s’STABLE • s’EVENT • User defined attributes other than ENUM_ENCODING are NOT supported UAH-CPE528

  15. Concurrent Signal Assignment Statements • Simple concurrent signal assignment statements are supported library IEEE; use IEEE.std_logic_1164.all; ENTITY aoi_csa is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END aoi_csa; ARCHITECTURE behavior OF aoi_csa IS SIGNAL sig1,sig2 : std_logic; BEGIN sig1 <= a AND b; sig2 <= c OR sig1; y <= NOT sig2; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY csa is PORT(a : IN std_logic; b : IN std_logic; y : OUT std_logic); END csa; ARCHITECTURE behavior OF csa IS BEGIN y <= a NOR b; END behavior; UAH-CPE528

  16. Conditional Signal Assignment Statements • Concurrent conditional signal assignment statements are supported - must end inelseclause library IEEE; use IEEE.std_logic_1164.all; ENTITY mux2 is PORT(a : IN std_logic; b : IN std_logic; sel : IN std_logic; y : OUT std_logic); END mux2; ARCHITECTURE behavior OF mux2 IS BEGIN y <= a WHEN (sel = '0') ELSE b WHEN (sel = '1') ELSE 'X'; END behavior; UAH-CPE528

  17. Selected Signal Assignment Statements • Concurrent selected signal assignment statements are supported library IEEE; use IEEE.std_logic_1164.all; ENTITY mux4 is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; d : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic); END mux4; ARCHITECTURE behavior OF mux4 IS BEGIN WITH sel SELECT y <= a WHEN "00", b WHEN "01", c WHEN "10", d WHEN "11", 'X' WHEN OTHERS; END behavior; UAH-CPE528

  18. Operators • Generally, if the numeric_bit and numeric_std packages are supported, the operators within them are supported • Arithmetic operators - “abs”, “+”, “-”, “*”, “/”, “rem”, “mod” library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY divider is PORT(divisor : IN unsigned(1 DOWNTO 0); dividend : IN unsigned(1 DOWNTO 0); quotient : OUT unsigned(1 DOWNTO 0)); END divider; ARCHITECTURE behavior OF divider IS BEGIN quotient <= dividend / divisor; END behavior; UAH-CPE528

  19. Operators (cont.) • Comparison operators - “>”, “<“, “<=“, “>=“, “=“, “/=“ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY compare is PORT(a : IN unsigned(3 DOWNTO 0); b : IN unsigned(3 DOWNTO 0); aleb : OUT boolean); END compare; ARCHITECTURE behavior OF compare IS BEGIN aleb <= (a <= b); END behavior; UAH-CPE528

  20. Operators (cont.) • Shift and conversion operators - “shift_left”, “shift_right”, “rotate_left”, “rotate_right”, “resize”, “to_integer”, “to_unsigned” library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY shift_4 is PORT(a : IN unsigned(3 DOWNTO 0); b : IN unsigned(1 DOWNTO 0); y : OUT unsigned(3 DOWNTO 0)); END shift_4; ARCHITECTURE behavior OF shift_4 IS BEGIN y <= shift_left(a,to_integer(b)); END behavior; UAH-CPE528

  21. Process Statements • Process statements are supported • Postponed processes (or postponed concurrent signal assignment statements) are NOT supported • Process statement can have either a sensitivity list or a WAIT statement • Sensitivity list is ignored for synthesis (by most tools) - thus, to avoid simulation mismatches, all signals which appear on the RHS should be in the sensitivity list • Only one WAIT statement per process is allowed and it must be the first statement in the process after BEGIN • Only the WAIT UNTIL syntax of the WAIT statement is supported WAIT UNTIL input1 = ‘1’; WAIT UNTIL clock’EVENT and clock = ‘1’; UAH-CPE528

  22. Process StatementsExample library IEEE; use IEEE.std_logic_1164.all; ENTITY aoi_process is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END aoi_process; ARCHITECTURE behavior OF aoi_process IS SIGNAL sig1 : std_logic; BEGIN comb : PROCESS(a,b,c,sig1) BEGIN sig1 <= a AND b; y <= not(sig1 or c); END PROCESS comb; END behavior; UAH-CPE528

  23. a b 0 c sig1 U y 0 5 10 15 20 Process StatementsIncomplete Sensitivity List library IEEE; use IEEE.std_logic_1164.all; ENTITY aoi_process is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END aoi_process; ARCHITECTURE behavior OF aoi_process IS SIGNAL sig1 : std_logic; BEGIN comb : PROCESS(a,b,c) BEGIN sig1 <= a AND b; y <= not(sig1 or c); END PROCESS comb; END behavior; UAH-CPE528

  24. Sequential Signal Assignment Statements • Various types of signal assignment statements inside a process statement (sequential signal assignment statements) are supported • IF statements • Case statements • Loop statement • Only For loops supported • Bounds must be specified as static values of an integer type • Exit and Next statements supported (without lables) UAH-CPE528

  25. Sequential IF Statements • IF statements are supported library IEEE; use IEEE.std_logic_1164.all; ENTITY xor_process is PORT(a : IN std_logic; b : IN std_logic; y : OUT std_logic); END xor_process; ARCHITECTURE behavior OF xor_process IS BEGIN comb : PROCESS(a,b) BEGIN IF((a = '1' and b = '0') OR (a = '0' and b = '1')) THEN y <= '1'; ELSE y <= '0'; END IF; END PROCESS comb; END behavior; UAH-CPE528

  26. Sequential Case Statements library IEEE; use IEEE.std_logic_1164.all; ENTITY mux4_process is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; d : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic); END mux4_process; ARCHITECTURE behavior OF mux4_process IS BEGIN comb : PROCESS(a,b,c,d,sel) BEGIN CASE sel IS WHEN "00" => y <= a; WHEN "01" => y <= b; WHEN "10" => y <= c; WHEN "11" => y <= d; WHEN OTHERS => y <= 'X'; END CASE; END PROCESS comb; END behavior; • Case statements are supported • Choices which include metalogical values are never taken UAH-CPE528

  27. Sequential Loop Statements • Only For loops with integer range are supported library IEEE; use IEEE.std_logic_1164.all; ENTITY shift4 is PORT(mode : IN std_logic; shift_in : IN std_logic; a : IN std_logic_vector(4 DOWNTO 1); y : OUT std_logic_vector(4 DOWNTO 1); shift_out : OUT std_logic); END shift4; ARCHITECTURE behavior OF shift4 IS SIGNAL in_temp : std_logic_vector(5 DOWNTO 0); SIGNAL out_temp : std_logic_vector(5 DOWNTO 1); BEGIN in_temp(0) <= shift_in; in_temp(4 DOWNTO 1) <= a; in_temp(5) <= '0'; comb : PROCESS(mode,in_temp,a) BEGIN FOR i IN 1 TO 5 LOOP IF(mode = '0') THEN out_temp(i) <= in_temp(i-1); ELSE out_temp(i) <= in_temp(i); END IF; END LOOP; END PROCESS comb; y <= out_temp(4 DOWNTO 1); shift_out <= out_temp(5); END behavior; UAH-CPE528

  28. Procedures and Functions • Procedures and Functions are supported - with limitations to allowed statement types • Procedures and functions may be in a package or in the declarative part of the architecture LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; PACKAGE logic_package IS FUNCTION majority(in1, in2, in3 : std_logic) RETURN std_logic; PROCEDURE decode(SIGNAL input : IN std_logic_vector(1 DOWNTO 0); SIGNAL output : OUT std_logic_vector(3 DOWNTO 0)); END logic_package; UAH-CPE528

  29. Procedures and Functions (cont.) PACKAGE BODY logic_package IS FUNCTION majority(in1, in2, in3 : std_logic) RETURN std_logic IS VARIABLE result : std_logic; BEGIN IF((in1 = '1' and in2 = '1') or (in2 = '1' and in3 = '1') or (in1 = '1' and in3 = '1')) THEN result := '1'; ELSIF((in1 = '0' and in2 = '0') or (in2 = '0' and in3 = '0') or (in1 = '0' and in3 = '0')) THEN result := '0'; ELSE result := 'X'; END IF; RETURN result; END majority; UAH-CPE528

  30. Procedures and Functions (cont.) PROCEDURE decode(SIGNAL input : IN std_logic_vector(1 DOWNTO 0); SIGNAL output : OUT std_logic_vector(3 DOWNTO 0)) IS BEGIN CASE input IS WHEN "00" => output <= "0001"; WHEN "01" => output <= "0010"; WHEN "10" => output <= "0100"; WHEN "11" => output <= "1000"; WHEN OTHERS => output <= "XXXX"; END CASE; END decode; END logic_package; UAH-CPE528

  31. Using Procedures and Functions LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE work.logic_package.all; ENTITY voter IS PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END voter; ARCHITECTURE maj OF voter IS BEGIN y <= majority(a,b,c); END maj; UAH-CPE528

  32. Using Procedures and Functions (cont.) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE work.logic_package.all; ENTITY decoder IS PORT(y : IN std_logic_vector(1 DOWNTO 0); g : OUT std_logic_vector(3 DOWNTO 0)); END decoder; ARCHITECTURE dec OF decoder IS BEGIN comb : PROCESS(y) BEGIN decode(y,g); END PROCESS comb; END dec; UAH-CPE528

  33. Tri-State Logic • Tri-state logic is infered when an object is assigned an IEEE Std. 1164 value ‘Z’ library IEEE; use IEEE.std_logic_1164.all; ENTITY tri_state4 is PORT(enable : IN std_logic; a : IN std_logic_vector(3 DOWNTO 0); y : OUT std_logic_vector(3 DOWNTO 0)); END tri_state4; ARCHITECTURE behavior OF tri_state4 IS BEGIN y <= a WHEN (enable = '1') ELSE "ZZZZ"; END behavior; UAH-CPE528

  34. Use of Don’t Cares (‘X’s) • IEEE Std. 1164 values of ‘X’ or ‘-’ can be used to specify “don’t care” conditions library IEEE; use IEEE.std_logic_1164.all; ENTITY not_xor is PORT(a : IN std_logic; b : IN std_logic; y : OUT std_logic); END not_xor; ARCHITECTURE behavior OF not_xor IS BEGIN comb : PROCESS(a,b) BEGIN IF((a = '1' and b = '0') OR (a = '0' and b = '1')) THEN y <= '1'; ELSE y <= 'X'; -- could also be ‘-’ END IF; END PROCESS comb; END behavior; UAH-CPE528

  35. After Clauses • Although not defined by the language, most simulator’s waveform windows do not show VHDL delta cycles adequately, if at all • Debugging large behavioral simulations before synthesis can be difficult if no delays are used - everything appears to happen simultaneously • List windows typically show delta cycles, but can be difficult to interpret • The solution is to put “dummy” delays in the behavioral descriptions using After clauses to “spread out” the events • After clauses are ignored for synhtesis CONSTANT delay : TIME := 5 ns; ... output <= input + 1 AFTER delay; UAH-CPE528

  36. Inferring Latches • If signals or variables are not assigned values in some conditional expressions of IF or Case statements, level-sensitive sequential logic might result ARCHITECTURE behavior OF mux3_seq IS BEGIN comb : PROCESS(a,b,c,sel) BEGIN CASE sel IS WHEN "00" => y <= a; WHEN "01" => y <= b; WHEN "10" => y <= c; WHEN OTHERS => --empty END CASE; END PROCESS comb; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY mux3_seq is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic); END mux3_seq; UAH-CPE528

  37. Avioding Latches library IEEE; use IEEE.std_logic_1164.all; ENTITY mux3 is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic); END mux3; ARCHITECTURE behavior OF mux3 IS BEGIN comb : PROCESS(a,b,c,sel) BEGIN CASE sel IS WHEN "00" => y <= a; WHEN "01" => y <= b; WHEN "10" => y <= c; WHEN OTHERS => y <= 'X'; END CASE; END PROCESS comb; END behavior; • Assigning values of “don’t care” (‘X’ or ‘-’) in these cases can avoid this UAH-CPE528

  38. Problems to AvoidInferring Latches in Complex Behaviors ARCHITECTURE rtl OF pc_comb IS SIGNAL pc : unsigned(3 DOWNTO 0); BEGIN one : PROCESS(dat_in, cntrl, pc) BEGIN CASE cntrl IS WHEN "01" => pc <= (pc + "0001"); WHEN "10" => pc <= pc; WHEN OTHERS => pc <= data_in; END CASE; END PROCESS one; DATA_OUT <= PC; END rtl; library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL; ENTITY pc_comb IS PORT(data_in : IN unsigned(3 DOWNTO 0); cntrl : IN unsigned(1 DOWNTO 0); data_out : OUT unsigned(3 DOWNTO 0)); END pc_comb; UAH-CPE528

  39. Problems to AvoidSynthesizing Asynchronous State Machines! library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY pc_comb2 is PORT(dat_in : IN unsigned(3 DOWNTO 0); cntrl : IN std_logic; data_out : OUT unsigned(3 DOWNTO 0)); END pc_comb2; ARCHITECTURE rtl OF pc_comb2 IS SIGNAL pc : unsigned(3 DOWNTO 0); BEGIN one : PROCESS(data_in, cntrl, pc) BEGIN CASE cntrl IS WHEN '1' => pc <= (pc + "0001"); WHEN '0' => pc <= data_in; WHEN OTHERS => pc <= "XXXX"; END CASE; END PROCESS one; dat_out <= pc; END rtl; UAH-CPE528

  40. Level Sensitive D Latch • Use IF statement without Else clause library IEEE; use IEEE.std_logic_1164.all; ENTITY d_latch is PORT(d : IN std_logic; clk : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END d_latch; ARCHITECTURE behavior OF d_latch IS BEGIN seq : PROCESS(d,clk) BEGIN IF(clk = '1') THEN q <= d; END IF; END PROCESS seq; qn <= not q; END behavior; UAH-CPE528

  41. Master-Slave D Latch(D Flip-Flop) library IEEE; use IEEE.std_logic_1164.all; ENTITY ms_latch is PORT(d : IN std_logic; clk : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END ms_latch; ARCHITECTURE behavior OF ms_latch IS SIGNAL q_int : std_logic; BEGIN seq1 : PROCESS(d,clk) BEGIN IF(clk = '1') THEN q_int <= d; END IF; END PROCESS seq1; seq2 : PROCESS(q_int,clk) BEGIN IF(clk = '0') THEN q <= q_int; END IF; END PROCESS seq2; qn <= not q; END behavior; Optimize UAH-CPE528

  42. Edge Sensitive D Flip-Flop • Clocks must be of BIT or STD_LOGIC type - metalogic values not allowed • Rising_edge() and Falling_edge() functions can be used to specify clock edge library IEEE; use IEEE.std_logic_1164.all; ENTITY d_ff is PORT(d : IN std_logic; clk : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END d_ff; ARCHITECTURE behavior OF d_ff IS BEGIN seq : PROCESS(clk) BEGIN IF(rising_edge(clk)) THEN q <= d; END IF; END PROCESS seq; qn <= not q; END behavior; UAH-CPE528

  43. Edge Sensitive D Flip-Flop (cont.) • Wait statement can be used library IEEE; use IEEE.std_logic_1164.all; ENTITY d_ff_w is PORT(d : IN std_logic; clk : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END d_ff_w; ARCHITECTURE behavior OF d_ff_w IS BEGIN seq : PROCESS BEGIN WAIT UNTIL rising_edge(clk); q <= d; END PROCESS seq; qn <= not q; END behavior; ARCHITECTURE behavior OF d_ff_w IS BEGIN seq : PROCESS BEGIN WAIT UNTIL clk = ‘1’; q <= d; END PROCESS seq; qn <= not q; END behavior; UAH-CPE528

  44. Edge Sensitive Flip-Flops library IEEE; use IEEE.std_logic_1164.all; ENTITY d_ff_pc is PORT(d : IN std_logic; clk : IN std_logic; pre : IN std_logic; clr : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END d_ff_pc; ARCHITECTURE behavior OF d_ff_pc IS BEGIN seq : PROCESS(clk,pre,clr) BEGIN IF(pre = '0') THEN q <= '1'; ELSIF(clr = '0') THEN q <= '0'; ELSIF(rising_edge(clk)) THEN q <= d; END IF; END PROCESS seq; qn <= not q; END behavior; • Preset and clear functions can be added • Asynchronous with respect to the clock UAH-CPE528

  45. Edge Sensitive Flip-Flops library IEEE; use IEEE.std_logic_1164.all; ENTITY d_ff_spc is PORT(d : IN std_logic; clk : IN std_logic; pre : IN std_logic; clr : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END d_ff_spc; ARCHITECTURE behavior OF d_ff_spc IS BEGIN seq : PROCESS(clk) BEGIN IF(rising_edge(clk)) THEN IF(pre = '0') THEN q <= '1'; ELSIF(clr = '0') THEN q <= '0'; ELSE q <= d; END IF; END IF; END PROCESS seq; qn <= not q; END behavior; • Preset and clear functions can be added • Synchronous with respect to the clock UAH-CPE528

  46. Finite State Machine Synthesis • State machines can be modeled as a combinational portion and a sequential portion • Both Mealy and Moore type state machines can be described • Most synthesis tools employ special algorithms to minimize state machines - thus standard procedures must be used to enable the tool to recognize the state machine Huffman FSM Model Primary Inputs Primary Outputs Combinational Logic Present State Next State Memory UAH-CPE528

  47. Next State Combinational Logic Next State Combinational Logic Output Combinational Logic Output Combinational Logic Mealy and Moore State Machine Models • A state machine has three basic parts • Next State Logic • Output Logic • Memory • The most straight-forward way to code a synthesizable state machine is to use one process per function Mealy Machine Model Moore Machine Model Primary Inputs Primary Inputs Primary Outputs Primary Outputs Present State Next State Present State Next State Memory Memory UAH-CPE528

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