Download
1 / 11
110 likes | 120 Views
This document discusses the testability and PDR (Pattern Definition and Reporting) in the FE-I4 Review at CERN. It provides information on test coverage, fault detections, and the use of functional tests in PDR. The document also explores testing methods and optimization of tests for better fault coverage.
E N D
Testability DOB & PDR Marlon Barbero / Tomasz Hemperek, Bonn University FE-I4 Review, CERN Nov. 3rd - 4th 2009
DOB testability • With scan chain, see previous talks. • status: “played with the tools” (ATPG Tetramax). • Coverage for stuck-up bits >99%. • ~ 80 patterns needed, or order 50 bits long each. for such a small block, this will be fast and with a high fault coverage. ----------------------------------------------- fault class code #faults ------------------------------ ---- --------- Detected DT 2061 Possibly detected PT 0 Undetectable UD 1 ATPG untestable AU 14 Not detected ND 0 ----------------------------------------------- total faults 2076 test coverage 99.33% ----------------------------------------------- Pattern Summary Report ----------------------------------------------- #internal patterns 79 #basic_scan patterns 79 -----------------------------------------------
PDR: ATPG vs. Functional Tests • ATPG: • Area. • Global signals (SEU problem). • Organization of scan chains (1/DC, 1/FE what to do if fail)? • 2 seeds for scan chain (up / down) and special top of DDC. • Functional: • PDR small enough for good functional testing. • Speed ok (see later). • Need to be done in all case! • Note that functional tests can be fed back to tool for coverage estimation.
What to test in PDR? • All memories. • ToT values. • Small / Big hit discrimination, all modes. • Neighbor logic. • Communication. • Readout. Not that big a region!
How to test • Use of stop mode, as you need to mask / unmask pixels during pixel injection. • e.g. (small / big or neighbors): • Disable clock. • Mask hits. • Send digital inject. • Send 1 clock. • Disable clock. • Send new mask. • Enable clock. • Send trigger. • Read data. pulse ck to regions
How fast • No serious estimate so far (should be done) but: • clk 40MHz. • highly parallel testing possible, but serial readout (the bottleneck?). • 2 masks operation (700clk) + reading data back (6×PairPix clk) + dig. pulse inject (50clk) + en/disable injection (30 clk) for complete FE ~ 80000 clk. • 500 such operations / second. • Should be no problem.
Can estimate coverage • Basic testing covered in test bench. • Might use digital tools to optimize tests (& test time) vs. fault coverage. after P&R test bench + run logic Feed simulation results to TetraMax
1st try with very simple test bench • Random hit injection. • 1 PDR, ~5ms of run time (1000 hits injected). • In this example, fault coverage needs optimization modify testing procedure. • Know where you need to improve coverage at single gate level. ----------------------------------------------- fault class code #faults ------------------------------ ---- --------- Detected DT 4994 Possibly detected PT 772 Undetectable UD 27 ATPG untestable AU 0 Not detected ND 577 ----------------------------------------------- total faults 6370 test coverage 84.82% ----------------------------------------------- Pattern Summary Report ----------------------------------------------- #internal patterns 0 #external patterns (PDR.par.evcd) 164442 #full_sequential patterns 164442 ----------------------------------------------- … sa1 UU OtherCnfg[0] sa1 UT LTIE_LTIEHI/Y sa0 DS LTIE_LTIEHI/Y sa1 UR RSTAND/B sa0 DS RSTAND/Y … Brings more rationality to your functional testing?
Backup • BACKUP
codes CODES:DT: detectedDR: detected robustlyDS: detected by simulationDI: detected by implicationPT: possibly detectedAP: ATPG untestable-possibly detectedNP: not analyzed-possibly detectedUD: undetectableUU: undetectable unusedUT: undetectable tiedUB: undetectable blockedUR: undetectable redundantAU: ATPG untestableAN: ATPG untestable-not detectedND: not detectedNC: not controlledNO: not observed
