8-bit MIPS Processor

1. 8-bit MIPS Processor EN160 Class Project May 2007

2. Finite State Machine Candice SheldonBrendan HargreavesEN160

3. Control logic for the CPU Fetch Decode Execute Module Objective

4. State2 = !S3S2!S1S0∙(Op=001000 + Op=100000) + !S3S2S1!S0 + !S3!S2S1S0 + !S3S2!S1!S0∙(Op=100000 + Op=101000 + Op=001000 + Op=000010) Design (Example: State2)

5. Standard Cells: 242 Nets: 254 Length of Nets: 182070.5 Vias: 847 Dimensions: 1187 x 2000 Area: 2,374,0002 Layout

6. Simulation Results Best Case (IRWrite<0>) Worst Case (AluSrcB<0>) 10.813ns 6.254ns Power ≈ 4μW

7. If we could draw a state machine diagram and export to a layout program If SPICE could simulate faster If S-Edit’s library system was better designed for collaboration If this could have been done in Verilog, VHDL, or even ABEL X X Export to Verilog Derive 24 Logic Equations X Covert to EDIF Draw 24+ Schematics X Wouldn’t It Be Nice… Draw State Diagram X Export as EDIF Import to S-Edit Import to L-Edit

8. ALU Control Unit and Input Multiplexor Mike Kadin EN160

9. ALUSrcA ALUSrcB ALUOp PC ReadInput1 ReadInput2 Instr Instr WriteBack ALU Support Hardware

10. Logic Design Multiplexors ALU Control Combo Logic

11. IC Layout • Design Assembled by L-Edit Automatic Placement and Routing • 602300 lambda2 (3.8E-8 m2 @ 500nm process) • Total Gates: 50 • Total Wire Length: 19790 lambda (~5mm)

12. Alucontrol0 Alucontrol1 Alucontrol2 2.4ns 1.6ns 1.0ns Timing and Power • ALU Control Power: .107mw • ALU Control Delays: • MUXes Power: .139mW • 2x1 Mux Delay: .88ns • 4x1 Mux Delay: 1.8ns • Total Gates: 50 Total Gates

13. Design Problems • VDD & GND • 2 Inputs from the Same Signal • Many Inputs Required Much Repeated Typing in the L-Edit Core Setup • Not Much Room for Creativity In Design

14. ALU design Nuno Alves Yiwen Shi

15. Perform different types of ALU calculation -- 8-bit ADD, SUB, AND, OR, SLT Compute the next PC address Objective of the ALU module Zero PCSource[0:1] PCWriteback[0:7] Instr[0:5] ALUInputA[0:7] ALUInputB[0:7] ALUOut[0:7] ALUControl[0:2]

16. Logic design 1/2 ALU kernel ADD/SUB module

17. ALUOut ShiftLeft2 MUX3

18. Area = 6809967.00 λ^2 = 425622.9735 um^2 Wirelength = 507588.5 λ = 126897.125 um #Standard Cells = 466 #Signals = 503 Prototype IC layout

19. Timing simulation and power • Take temp=70 for example

20. Modularity = smaller designs Simulations agree with theoretical results It is unfortunate than S-Edit, L-Edit and Spice are not combined into a single package Very hard to debug schematics in S-Edit What we have learned…

21. Register File Luis Camacho

22. WRITE ENABLE READ REG 1 READ DATA 1 READ REG 2 READ DATA 2 WRITE REGISTER DATA CLK Register File Module • Reads up to 2 register (same time) • Writes into a destination register • Uses (8) 8-bit registers • (8) I/O pins A B

23. Register File Schematic 8-bit Register 8x8 Multiplexer Enable write destination register

24. D Q Q’ CLK Timing Simulations 3x8 Decoder 8-bit Register • 0 1 0 1 0 1 0 • 1 1 0 0 1 1 0 0 • 1 1 1 1 0 0 0 0

25. R$0 R$1 R$2 R$3 R$4 R$5 R$6 R$7 Out[0:7] Add[0:2] Timing Simulations 8x8 Multiplexer 10101010 100

26. Register File - Timing Simulation INPUT: 10101010 READ R$1 READ R$0 [6-11ns] [9-10ns] [13-18ns]

27. Layout Analysis

28. Comments • Lessons learnt: • Tristate buffer vs Multiplexer • Performance of SmartSpice vs T-Spice • Alternative way to ground Register 0 • Things that could have speed up simulations: • Feature to connect ports (one-to-many) • Better way to export SmartView figures

29. Integration Brian Reggiannini

30. CPU Floorplan

32. Area Total area 4234.5 x 6555.0 λ2 λ = 250 nm Total area 1.73 mm2 1346 standard cells Wire Length 2305973.5 λ = 57.6 cm Layout

34. Functional Verification

35. Variable clock period 30 ns for fetch and write-back states 65 ns for execution state Overall throughput 6 short cycles 1 long cycle 245 ns per instruction 4.1M instructions/second ALU execution is critical section FSM contributes most latency Average power consumption 10.8 mW Timing and Power Analysis