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Effective TARO Pattern Generation

This paper presents an effective TARO test pattern generation algorithm for detecting faults through reachable outputs, with thorough evaluation, experimental results, and conclusions. It outlines methodologies for identifying fault-output pairs, generating tests for undetected pairs, and achieving high TARO coverage for reliable computing. The approach is demonstrated on ELF-Murphy chips with detailed analysis and comparisons between transition and TARO tests.

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Effective TARO Pattern Generation

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  1. Effective TARO Pattern Generation Intaik Park Ahmad Al-Yamani Edward J. McCluskey Sponsored by NFS and LSI logic Stanford University Center for Reliable Computing

  2. Outline • Introduction • Preliminaries • Algorithm • Evaluation • Experimental Result • Conclusion

  3. Test escapes of ELF-Murphy chips • 100% SSF test • escapes • 100% transition test • escapes • TARO test (Transition fault propagated to All Reachable Output) • No escape

  4. Definitions • Reachable outputs : Outputs through which a fault can be propagated and be observed • Observable faults : Faults that an output can observe • Fault-output pair : A pair of fault site and one of its reachable output

  5. Example of fault-output pair a 1 b 2 c 3 4 d Fault site Output (PO+FF) fault-output pair

  6. Finding fault-output pairs 1. Observable faults for all outputs • by logical cone tracing • or by output mask setup 2. Reachable outputs for all fault sites • from observable faults 3. Fault site paired with a reachable output  fault-output pair

  7. TARO generation algorithm • Assign fault-output pairs • Only those that could be assigned at the same time • Use output masks • To control to which output a fault will be propagated

  8. TARO generation algorithm (contd.) • Generate tests for undetected • fault-output pairs • Exclude detected f-o pairs • Use output mask • - Control what output will observe the fault a 1 b 2 c 3 4 d Fault site Output (PO+FF) Detected f-o pair Undetected f-o pair

  9. TARO generation algorithm (contd.) • Assigned fault-output pairs: • fault a  output 1 • fault c  output 3 • fault d  output 3 • Output masks: • output 2, 4 • Fault b excluded a 1 b 2 c 3 4 d Fault site Output (PO+FF) Detected f-o pair Undetected f-o pair Assigned f-o pair

  10. TARO generation flowchart Start Find fault-output pairs ATPG with masks Fault simulation on each output All f-o pair detected? No Assign f-o pairs / masks Initial ATPG without masks Yes End

  11. TARO coverage • Traditional transition fault coverage • Not sufficient for TARO evaluation • Test metric required • To reflect number of reachable outputs used for each fault site # reachable outputs used Weight of fault = # total reachable outputs Σ weights of detected faults TARO coverage = # all faults

  12. ELF35 cores • 4 combinational cores (1 translator, 3 data paths) • 2 sequential cores (full-scanned 2901 processors)

  13. Test escapes of ELF35 * Number of escapes

  14. ELF35 Transition vs TARO test

  15. Conclusion • TARO tests generation method • + Using existing ATPG tool • + Very thorough test quality (no escapes) • - Long generation time • - Large pattern size • TARO  very thorough test • Sample-based quality assurance test • Metric to evaluate other tests • To which output a fault is sensitized matters

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