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Reduction only needed for p+p and light A+A calibration runs

EMCal/RICH Trigger Layout. Reduction only needed for p+p and light A+A calibration runs. At high transverse momenta: photons, electrons from W-decay, Drell Yan electrons, charged hadrons At low transverse momenta : Electrons from heavy flavor decays. Generate primitives for level 2

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Reduction only needed for p+p and light A+A calibration runs

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  1. EMCal/RICH Trigger Layout Reduction only needed for p+p and light A+A calibration runs At high transverse momenta: photons, electrons from W-decay, Drell Yan electrons, charged hadrons At low transverse momenta : Electrons from heavy flavor decays Generate primitives for level 2 (Ring count in RICH) Electron trigger at low transverse momenta -> access to rare probes: Global Et? Possible Triggers: Kenneth Barish 11 February, 2000

  2. Current Layout EMC FEM Boards RICH x 172 x 3 Ersatz Trigger Cards AMU/ADC Module NIM Logic Trigger Module 256 8bit FADC words RICH Local Level 1 to GL1 to GL1

  3. EMCal Front End Board and Trigger Card Input: 172 Supermodules with 12x12 towers FEM Boards (input from 12x12 EMCal towers) x 172 ... Ersatz Trigger Card to NIM logic or Local Level 1

  4. RICH/EMCal Layout Option #1 EMC RICH FEM Boards x 172 ... AMU/ADC Module Ersatz Trigger Cards Trigger Module x 8 (2 for each threshold) MuId ROC 256 8bit FADC words o Use MuId ROC to feed ETC output into data stream and trigger system o Place data receiver module for EMCal data and electron trigger board into RICH local level 1 board for easy access to RICH data. RICH Local Level 1 to GL1 Are RICH primitives (Adjacency check on Tiles, Ring Sums) still required input at Level 2 or can this be generated at level 2 based on increased processing power? If yes, when will the RICH local level 1 be built?

  5. Possible EMCal LL1 Logic 172 EMCal Channels FPGA’s GL-1 East Arm 256 RICH Channels West Arm

  6. Possible Logic Inside FPGA’s RICH EMCal RICH EMCal RICH EMCal RICH EMCal RICH EMCal

  7. RICH/EMCal Layout Option #2 EMC RICH FEM Boards x 172 ... AMU/ADC Module Ersatz Trigger Cards Trigger Module x 8 (2 for each threshold) MuId ROC x 8 (for 256 trigger tiles in 8 FE crates) GLink GLink New RICH/EMCal Local Level 1 o Use MuId ROC for prompt .OR. and to transfer ETC output via Glink. o Combined RICH/EMCal local level 1 crate. Use existing design (8Rx) as data receiver cards. New Electron Trigger Board. to GL1

  8. EMC EMC/RICH Funding Prospects FEM Boards US/J RICH RBRC x 172 ... 160k Ersatz Trigger Cards AMU/ADC Module (JFY99/00) (funds req. JFY00) x 8 (2 for each threshold) Trigger Module MuId ROC (50k) x 8 (for 256 trigger tiles in 8 FE crates) GLink GLink New RICH/EMCal Local Level 1 UCR (FY00/01) (100k) o Use MuId ROC for prompt .OR. and to transfer ETC output via Glink. o Combined RICH/EMCal local level 1 crate. Use existing design (8Rx) as data receiver cards. New Electron Trigger Board. to GL1

  9. Outstanding Issues • LVL-1 • EMCal • Rejection power needed • Number of EMCal trigger elements (possible 172) • How to realize Et trigger • Threshold issues • RICH • Number of RICH trigger elements (possible 256) • Overlapping tiles? • FADC or threshold? • Rejection power needed • LVL-2 • Is ring count needed from LVL1? • Electron candidates needed from LVL1. (Brian Cole) • What information needs to be in data streme from LVL1 for LVL2? • Offline • What information needs to be in data streme

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