R&D work on gigabit optical link for ATLAS ID readout upgrade at SMU

1. R&D work on gigabit optical link for ATLAS ID readout upgrade at SMU Objectives: Evaluate the GOL chip in an optical link system and perform characteristic measurements (jitter, bit error rate, etc). (done in 2006) Irradiate the GOL up to 100 Mrad and measure SEE, TID. (done in Jan./Feb.2007) Continue evaluation on link components in radiation : VCSELs, fibers (in progress in 2007) Work with LBNL and UCSC to develop a 1.6 gigabit optical link to readout the test stave. (in progress in 2007) Participating in the development of a baseline optical link for the ID readout upgrade. Work with groups developing ABCNext, LOC, GBT and the Versatile link (module). (in progress for 2007 – 2009). Manpower: One FTE in a team of three FTEs, two RAs and two faculty members. Report: R&D work for ID upgrade May 3, 2007 @ UCSC

2. 32 bits/40 MHz 16 bits/80 MHz Test results on the GOL in 2006 – 2007 (1) • The test system designed and constructed for in-lab and irradiation tests: A big board for a small chip: For in-lab (BER, jitter and power-up schemes) and irradiation (gamma, proton and neutron) tests. The VCSEL is mounted 2 mm away from the GOL. The LC connector is 4×4 mm2 cross, and 50 mm boot length. The fiber is 1.6 mm OD. GOL: 13×13mm2×1.7mm, ~400 mW. The actual PCB space needed for in the actual application will be less than 20 mm × 30 mm (the red mark). The upper 3U crate hosts boards in the beam (gamma or proton). The lower 6U crate hosts controlling and DAQ boards. The master PC can be placed 40 meters away, connecting with USB. LabVIEW based GUI. Report: R&D work for ID upgrade May 3, 2007 @ UCSC

3. Test results on the GOL in 2006 – 2007 (2) • In-lab characterization tests on the GOL: • Bit Error Rate (BER): • Tr-225ps, Tf-245ps. • Eye mask test. • Power-up schemes studied and found to be reliable. • The jitter tests: • GOL reference clock jitter transfer function: • Clock jitter cutoff at about 1 MHz. • Complies with the adapted IEEE standards. • Low frequency jitter (noise) source • at the system level needs to be • watched for. • GOL-TLK optical link jitter tolerance: • Jitter tolerance complies with the IEEE • standard. • This plot specifies the transmitter • reference clock jitter to be below the • blue line to achieve a BER less than 10-12. BER > 10-12 BER < 10-12 Report: R&D work for ID upgrade May 3, 2007 @ UCSC

4. Test results on the GOL in 2006 – 2007 (3) • Irradiation tests on GOL: • Source: 230 MeV proton. • Tests: TID up to 106 Mrad (Si); SEE cross section (probability). • Results: TID: • No supply current increase during the irradiation. GOL functions error free immediately after the beam is off, very small change in eye diagram and jitter.  survives the TID test of 106 Mrad(Si) SEE:  very small SEE cross section. Eye diagram: before (left) and after Report: R&D work for ID upgrade May 3, 2007 @ UCSC

5. Test results on VCSEL and fiber in 2006 – 2007 • Tests on fiber and VCSEL. The Fiber: • Infinicor SX+ 50/250m/1.6mm MM 10G fiber from Corning. Germanium doped. • Tested wit Gamma (Co-60) and Proton (230 MeV, 1.9×1013 proton/cm2). • Very small light loss at low flux (dose rate). Big loss at high flux but anneals very quickly (within 1 hour) back. • Very promising for LHC upgrade. • More tests with gamma needed. The VCSEL: • Two HFE6192-562 (10G LC w/ 50 ohm flex) from Finisar tested . • Irradiated with 230 MeV proton, 1.9×1013 proton/cm2. • The VCSELs are biased during irradiations. • Eye diagram – see plots and table. • Looks very promising but more tests needed. L1, before irradiation Report: R&D work for ID upgrade May 3, 2007 @ UCSC L1, after irradiation

6. Conclusions on the GOL, VCSEL and fiber evaluation • GOL complies with the adapted (to 1.6 Gbps) IEEE standard for Gigabit Ethernet (1.25 Gbps). • GOL is tested to be rad-resistant up to 106 Mrad (Si). • The SEE probability is measured to be 1.1×10-13 for link frame loss and 1.1×10-14 for single bit flip.  The GOL chip is a good candidate for 1.6 Gbps optical link, rad-hard to the ID requirement. • We have preliminary candidates for the VCSEL and the fiber. Report: R&D work for ID upgrade May 3, 2007 @ UCSC

7. Plans for 2007 and 2008 • Issues on a gigabit optical link architecture: • Rad-hard serializer + TOSA (driver, VCSEL), • Rad-hard fiber, • Reference clock jitter control (cleaning), • Input data bit-to-bit skew control, • Reliability and single point failure prevention. • To address the above issues, we plan to: • Collaborate with LBNL and UCSC to construct a GOL based prototype link to readout the test stave. • To study gigabit link system issues with the ABCNext (ABCD for now) upstream electronics, with the QPLL clock jitter cleaner. • A dual link system will be investigated to address • The single point failure, • The SEE • CERN QPLL chip will be used as the clock cleaner. • Do more irradiation tests on fiber and VCSEL to identify candidates for a multi-gigabit optical link for SLHC ID readout upgrade. • Carry out reliability tests on the GOL, TOSA to provide info about the redundancy in the link. • Investigate the LOC and the GBT as the serializer chip when they become available for higher bandwidth link. Report: R&D work for ID upgrade May 3, 2007 @ UCSC

8. Our design of the GOL based prototype optical link (1) fiber TOSA data (32) GOL Delay lines fiber connector LVDS  CMOS clock VCSEL Delay line + QPLL Control logic The transmitter board. The output can be chosen to go through TOSA (CERN rad-hard versatile link) or a VCSEL to avoid failures in the optical device and fiber. The delay line in the data bus is used to address the bit-to-bit skew problem. In ABCnext, this delay will be implememented. Report: R&D work for ID upgrade May 3, 2007 @ UCSC

9. Our design of the GOL based prototype optical link (2) data (32) TLK 2500 fiber ROSA 1:2 deMUX CMOS  LVDS connector clock PIN+TIA+LA The receiver board Report: R&D work for ID upgrade May 3, 2007 @ UCSC

10. Budget (for 2008) Report: R&D work for ID upgrade May 3, 2007 @ UCSC