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Overview. Why VLSI? Moore’s Law. Why FPGAs? The VLSI and system design process. Why VLSI?. Integration improves the design: lower parasitics = higher speed; lower power; physically smaller. Integration reduces manufacturing cost-(almost) no manual assembly. VLSI and you.
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Overview • Why VLSI? • Moore’s Law. • Why FPGAs? • The VLSI and system design process.
Why VLSI? • Integration improves the design: • lower parasitics = higher speed; • lower power; • physically smaller. • Integration reduces manufacturing cost-(almost) no manual assembly.
VLSI and you • Microprocessors: • personal computers; • microcontrollers. • DRAM/SRAM/flash. • Audio/video and other consumer systems. • Telecommunications.
Moore’s Law • Gordon Moore: co-founder of Intel. • Predicted that number of transistors per chip would grow exponentially (double every 18 months). • Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles.
The cost of fabrication • Current cost: $2-3 billion. • Typical fab line occupies about 1 city block, employs a few hundred people. • New fabrication processes require 6-8 month turnaround. • Most profitable period is first 18 months-2 years.
Cost factors in ICs • For large-volume ICs: • packaging is largest cost; • testing is second-largest cost. • For low-volume ICs, design costs may swamp all manufacturing costs. • $10 million-$20 million.
Field-programmable gate arrays • FPGAs are programmable logic devices: • Logic elements + interconnect. • Provide multi-level logic. LE Interconnect network LE LE LE LE LE
FPGAs and VLSI • FPGAs are standard parts: • Pre-manufactured. • Don’t worry (much) about physical design. • Custom silicon: • Tailored to your application. • Generally lower power consumption.
Standard parts vs. custom • Do you build your system with an FPGA or with custom silicon? • FPGAs have shorter design cycle. • FPGAs have no manufacturing delay. • FPGAs reduce inventory. • FPGAs are slower, larger, more power-hungry.
Challenges in system design • Multiple levels of abstraction: logic to CPUs. • Multiple and conflicting constraints: low cost and high performance are often at odds. • Short design time: Late products are often irrelevant.
FPGA-based system design The system design process • May be part of larger product design. • Major levels of abstraction: • specification; • architecture; • logic design; • circuit design; • layout.
Dealing with complexity • Divide-and-conquer: limit the number of components you deal with at any one time. • Group several components into larger components: • transistors form gates; • gates form functional units; • functional units form processing elements; • etc.
Hierarchical name • Interior view of a component: • components and wires that make it up. • Exterior view of a component = type: • body; • pins. cout Full adder sum a b cin
Add2.a Add1.a Instantiating component types • Each instance has its own name: • add1 (type full adder) • add2 (type full adder). • Each instance is a separate copy of the type: cout Add2(Full adder) Add1(Full adder) sum sum a a b b cin cin
A hierarchical logic design box1 box2 x z
Net list: net1: top.in1 in1.in net2: i1.out xxx.B topin1: top.n1 xxx.xin1 topin2: top.n2 xxx.xin2 botin1: top.n3 xxx.xin3 net3: xxx.out i2.in outnet: i2.out top.out Component list: top: in1=net1 n1=topin1 n2=topin2 n3=topine out=outnet i1: in=net1 out=net2 xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet Net lists and component lists
Component hierarchy top i1 xxx i2
Hierarchical names • Typical hierarchical name: • top/i1.foo component pin
Layout and its abstractions • Layout for dynamic latch:
Mixed schematic inverter
Levels of abstraction • Specification: function, cost, etc. • Architecture: large blocks. • Logic: gates + registers. • Circuits: transistor sizes for speed, power. • Layout: determines parasitics.
Circuit abstraction • Continuous voltages and time:
Digital abstraction • Discrete levels, discrete time:
Register-transfer abstraction • Abstract components, abstract data types: 0010 + 0001 + 0011 0100
Top-down vs. bottom-up design • Top-down design adds functional detail. • Create lower levels of abstraction from upper levels. • Bottom-up design creates abstractions from low-level behavior. • Good design needs both top-down and bottom-up efforts.
English Throughput, design time Executable program Function units, clock cycles function Sequential machines cost Literals, logic depth Logic gates nanoseconds transistors microns rectangles Design abstractions specification behavior register- transfer logic circuit layout
FPGA design • FPGA manufacturer creates an FPGA fabric; system designer uses the fabric. • FPGA fabric design issues: • Study sample user designs. • Select interconnect topology. • Create logic element structures. • Design circuits, layout.
Why do we care about layout? • We won’t design layout. • Layout determines: • Logic delay. • Interconnect delay. • Energy consumption. • We want to understand sources of FPGA characteristics.
Design validation • Must check at every step that errors haven’t been introduced-the longer an error remains, the more expensive it becomes to remove it. • Forward checking: compare results of less- and more-abstract stages. • Back annotation: copy performance numbers to earlier stages.