ECE 546 Introduction

1. ECE 546 Introduction Spring 2014 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu

2. Future System Needs and Functions Digital Wireless Auto MEMS Analog, RF Consumer Computer High-speed Digital High bandwidth

3. Demand in the Information Age Required media and the amount of information 100 Mbps per home Source: ITRCS

4. PCI • PC Interface • For external cards • Graphics, Network, Sound, etc… • Parallel

5. PCI-Express • Computer Expansion Card Standard • Replaced older PCI • Based on serial links • Capacity up to 1 Gb/s • V3.0 scheduled for 2010

6. Universal Serial Bus (USB) • Interfaces devices to computers • No rebooting • Low power • No need for external power supply • 480 Mb/s

7. IDE • Expansion Card Standard • Replaced older PCI • Based on serial links • Capacity up to 1 Gb/s • V3.0 scheduled for 2010 7

8. Serial - ATA • Storage interface • Replaces older parallel ATA or IDE • Based on serial links • Capacity up to 3 Gb/s • Hot swapping capability

9. Computer Interconnections

10. Motherboards and Backplanes 10

11. Cables and Transmission Lines twisted pairs coaxial

12. Cable Specifications

13. Semiconductor Technology Trends

14. Global Wiring w/o Repeaters Global Wiring w Repeaters Local Wiring Gate Delay Signal Delay Trend gates delay Signal Delay interconnect delay Delay for Metal 1 and Global Wiring versus Feature Size Source: ITRS roadmap 2004

15. The Interconnect Bottleneck Al 3.0 mW -cm Cu 1.7 mW -cm SiO2 k = 4.0 Low kk = 2.0 Al & Cu .8m Thick Al & Cu Line 43m Long

16. MOS Technology Trends

17. Interconnect • Total interconnect length (m/cm2) – active wiring only, excluding global levels will increases: • Interconnect power dissipation is more than 50% of the total dynamic power consumption in 130nm and will become dominant in future technology nodes • Interconnect centric design flows have been adopted to reduce the length of the critical signal path

18. 5-Layer Interconnect Technology 0.25 mm Vertical parallel-plate capacitance 0.05 fF/mm2 Vertical parallel-plate capacitance (min width) 0.03 fF/mm Vertical fringing capacitance (each side) 0.01 fF/mm Horizontal coupling capacitance (each side) 0.03 Source: M. Bohr and Y. El-Mansy - IEEE TED Vol. 4, March 1998

19. Integrated Circuit Wiring Vertical parallel-plate capacitance 0.05 fF/mm2 Vertical parallel-plate capacitance (min width) 0.03 fF/mm Vertical fringing capacitance (each side) 0.01 fF/mm Horizontal coupling capacitance (each side) 0.03

20. Chip-Level Interconnect Delay Logic threshold Logic threshold

21. Package-Level Complexity - Up to 16 layers - Hundreds of vias - Thousands of TLs - High density - Nonuniformity

22. Signal Integrity Ideal Common Noisy

23. Signal Integrity Crosstalk Dispersion Attenuation Reflection Distortion Loss Delta I Noise Ground Bounce Radiation

24. IC on Package

25. Mixed Signal Noise •  Simultaneous switching and inductance (Leff) •  Leff is f( current magnitude and direction) •  Interactions between noise generated by power/ground and signal paths

26. Power-Supply Noise • Power-supply-level fluctuations • Delta-I noise • Simultaneous switching noise (SSN) • Ground bounce

27. Power Distribution Problem Low Frequency High Frequency At high frequencies, Wire B is a transmission line and ground connection is no longer the reference voltage

28. On-Chip Power and Ground Distribution • Distribution Network for Peripheral Bonding • Power and ground are brought onto the chip via bond pads located along the four edges • Metal buses provide routing from the edges to the remainder of the chip

29. Dual-in-Line (DIP) Package • Mounted on PWB in pin-through-hole (PTH) configuration • Chip occupies less than 20% of total space • Lead frame with large inductance

30. Packages & Packaging Trends Thermal Package Quad Flat Pack MCM

31. Stacked Wire Bonds

32. Ceramic Substrate

33. Area Bonding with Flip Chip Bumped Die Package Body Pins • Minimizes IR drops between gates • Minimizes interconnection inductance

34. 3D IC and TSV • Make use of third dimension • Can scale several orders of magnitude (10/cm2 to 108/cm2) • Minimize interconnection length  reduce delay • More design flexibility

35. 3D Integration

36. Thru Silicon Vias

37. TSV-Based Products STMicro CMOS image sensor in WLP/TSV package Sony Video / DSC camera with BSI CMOS image sensors Elpida’s 3D TSV stacked DRAM memory There are currently about 15 different 3D-IC pilot lines worldwide

38. TSV and 3D-IC • Make use of third dimension • Can scale several orders of magnitude (10/cm2 to 108/cm2) • Minimize interconnection length  reduce delay • More design flexibility Advantages New Architectures Issues • Memory • Logic • Analog • MEMS • 3D Infrastructure & supply chain • I/O Standardization • EMI • Thermal management and reliability

39. Silicon Interposer

40. Silicon Interposer

41. Measurements VNA: S-parameter Spectrum Analyzer Time-domain simulation Eye diagram

42. Tools for Physical Design * Schematic editor * Circuit level simulator * Layout editor * Placement & routing * Design rule checker * Netlist extractor * Layout vs Schematic * Libraries * Design verification * Electromagnetic analysis

43. State-of-the-Art in Extraction INDUCTANCE * MoM- BEM (2D) * FEM (2D) * PEEC (3D) * Fast Multipole CAPACITANCE * MoM- BEM * FEM * Fast Multipole Main Challenge: 3D inductance extraction is computationally expensive.

44. Circuit Simulation Chip Board/Module Y(t) v(t) = I(t) Given, Y and I, find v * SPICE * Asymptotic Waveform Evaluation * Complex Frequency Hopping * Passive Multipoint Matching Method * Latency Insertion Method

45. Why SPICE ?  Established platform  Powerful engine  Source code available for free  Extensive libraries of devices  New device installation procedure straightforward

46. SPICE Directory Structure

47. Interconnect Simulation Application • New Interconnects: • 3D Interconnect (System In Package) • package-intermediated interconnects Chip-Package-Board Co-Design • Power Ground Network: • It will greatly affect the performance of the chip design: • Voltage (IR) drops on VDD nets • ground bounce on VSS nets • High currents in the power grids  Electromigration effect Power Ground Network Design

48. Repeated Simulation of the Package/Board Super Fast Simulation Repeated Simulation of the Package/Board Super Fast Simulation Chip-Package Co-Design Source: Joel Mcgrath, “Chip/package co-design: The bridge between chips and systems “, Advanced Packaging Magazine June, 2001

49. Repeated Simulation of the P/G network  Super Fast Simulation Power Ground Network Design Flow

50. Deep Submicron Timing Closure Unbounded design iterations resulting from unpredicted timing violations - 0.25 microns and lower - 2 to 20 iterations - mismatch between logic and physical designs - greater timing variations - dominated by interconnects - inductive and capacitive coupling - slows time-to-market