High Abstraction Modeling

1. High Abstraction Modeling Rafi Spigelman - Intel

2. High Level Models • Should describe & model the Arch and the uArch “from 20000 feet” • Fast & Lean. Should Include only what’s required for Arch & uArch “concept” exploration and validation • Can be used for early validation of Arch & uArch concepts and configurations. • Performance, Functionality, Formal Property validation • Building verification infrastructure • HLM is for architects. It can be later used as a reference model for RTL

3. Can HLM replace RTL • Nop – HLM is not detailed enough • Make it as detailed as RTL and you get an RTL… • We need RTL details for the design • The gap between HLM and gate level netlist is too high (for both practical manual and synthesis design) • RTL is “just right” • We need RTL models for functional silicon debug and for functional production testing • Gate Level simulations too slow and “too detailed” for efficient debug • HLM models are not detailed enough