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Lecturer PSOE Dan Garcia cs.berkeley/~ddgarcia

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 28 – Single Cycle CPU Control II. Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia. DARPA $s drying up…ouch! .

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Lecturer PSOE Dan Garcia cs.berkeley/~ddgarcia

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  1. inst.eecs.berkeley.edu/~cs61cCS61C : Machine Structures Lecture 28 – Single Cycle CPU Control II Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia DARPA $s drying up…ouch! “I'm worried and depressed,” – David Patterson, president of the ACM. There is a significant shift of $ from “Blue Sky” research to military contractors. This is a significant shift, mostly for the worse. www.nytimes.com/2005/04/02/technology/02darpa.html?

  2. Datapath Review: Single cycle datapath • 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic • Control is the hard part • MIPS makes that easier • Instructions same size • Source registers always in same place • Immediates same size, location • Operations always on registers/immediates Processor Input Control Memory Output

  3. add sub ori lw sw beq jump RegDst 1 1 0 0 x x x ALUSrc 0 0 1 1 1 0 x MemtoReg 0 0 0 1 x x x RegWrite 1 1 1 1 0 0 0 MemWrite 0 0 0 0 1 0 0 nPCsel 0 0 0 0 0 1 0 Jump 0 0 0 0 0 0 1 ExtOp x x 0 1 1 x x ALUctr<2:0> Add Subtract Or Add Add x Subtract 31 26 21 16 11 6 0 R-type op rs rt rd shamt funct add, sub immediate I-type op rs rt ori, lw, sw, beq J-type op target address jump A Summary of the Control Signals (2/2) See func 10 0000 10 0010 We Don’t Care :-) Appendix A op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010

  4. 31 26 25 0 J-type jump op target address The Single Cycle Datapath during Jump • New PC = { PC[31..28], target address, 00 } Instruction<31:0> Jump= Instruction Fetch Unit nPC_sel= Rd Rt <0:15> <0:25> <21:25> <16:20> <11:15> Clk RegDst = 1 0 Mux Rt Rs Rd Imm16 TA26 ALUctr = Rs Rt RegWr = MemtoReg = 5 5 5 busA Zero MemWr = Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = ExtOp =

  5. 31 26 25 0 J-type jump op target address The Single Cycle Datapath during Jump • New PC = { PC[31..28], target address, 00 } Instruction<31:0> Jump=1 Instruction Fetch Unit nPC_sel=0 Rd Rt <0:15> <0:25> <21:25> <16:20> <11:15> Clk RegDst = x 1 0 Mux Rt Rs Rd Imm16 TA26 ALUctr =x Rs Rt RegWr = 0 MemtoReg = x 5 5 5 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc = x ExtOp = x

  6. 31 26 25 0 J-type jump Inst Memory Adr Adder Mux Adder op target address Instruction Fetch Unit at the End of Jump • New PC = { PC[31..28], target address, 00 } Jump Instruction<31:0> nPC_sel Zero nPC_MUX_sel How do we modify thisto account for jumps? 4 00 0 PC 1 Clk imm16

  7. 31 26 25 0 J-type jump Inst Memory Adr Adder Mux Mux Adder op target address Instruction Fetch Unit at the End of Jump • New PC = { PC[31..28], target address, 00 } Jump Instruction<31:0> nPC_sel Zero • Query • Can Zero still get asserted? • Does nPC_sel need to be 0? • If not, what? nPC_MUX_sel 00 4 00 1 TA26 PC 0 4 (MSBs) 0 Clk 1 imm16

  8. Inst31 Inst30 Inst29 Inst28 Inst27 Inst26 Inst25 Inst01 Inst00 Build CL to implement Jump on paper now Jump

  9. Review: Finite State Machine (FSM) • Statesrepresent possible output values. • Transitionsrepresent changes between statesbased on inputs. • Implementwith CL andclocked registerfeedback.

  10. Finite State Machines extremely useful! • They define • How output signals respond to input signals and previous state. • How we change states depending on input signals and previous state • The output signals could be our familiar control signals • Some control signals may only depend on CL, not on state at all… • We could implement very detailed FSMs w/Programmable Logic Arrays

  11. Taking advantage of sum-of-products • Since sum-of-products is a convenient notation and way to think about design, offer hardware building blocks that match that notation • One example isProgrammable Logic Arrays (PLAs) • Designed so that can select (program) ands, ors, complements after you get the chip • Late in design process, fix errors, figure out what to do later, …

  12. • • • inputs ORarray ANDarray productterms outputs • • • Programmable Logic Arrays • Pre-fabricated building block of many AND/OR gates • “Programmed” or “Personalized" by making or breaking connections among gates • Programmable array block diagram for sum of products form • Or Programming: • How to combine product terms? • How many outputs? • And Programming: • How many inputs? • How to combine inputs? • How many product terms?

  13. Enabling Concept • Shared product terms among outputs F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A example: input side: 3 inputs 1 = uncomplemented in term 0 = complemented in term – = does not participate personality matrix Product inputs outputs term A B C F0 F1 F2 F3AB 1 1 – 0 11 0B'C – 0 1 0 0 0 1AC' 1 – 0 0 1 0 0B'C' – 0 0 1 0 1 0A 1 – – 1 0 0 1 output side: 4 outputs 1 = term connected to output 0 = no connection to output reuse of terms; 5 product terms

  14. Before Programming • All possible connections available before “programming”

  15. B C A AB B'C AC' B'C' A F0 F1 F2 F3 After Programming • Unwanted connections are "blown" • Fuse (normally connected, break unwanted ones) • Anti-fuse (normally disconnected, make wanted connections)

  16. A B C D AB A'B' CD' C'D AB+A'B' CD'+C'D Alternate Representation • Short-hand notation--don't have to draw all the wires • X Signifies a connection is present and perpendicular signal is an input to gate notation for implementing F0 = A B + A' B' F1 = C D' + C' D

  17. Instruction<31:0> nPC_sel Instruction Fetch Unit Rd Rt <0:15> <16:20> <11:15> <21:25> Clk RegDst 1 0 Mux Rt Rs Rd Imm16 Rs Rt RegWr ALUctr Zero 5 5 5 MemWr MemtoReg busA Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk 32 Mux Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc ExtOp Peer Instruction • MemToReg=‘x’ & ALUctr=‘sub’. SUB or BEQ? • ALUctr=‘add’. Which 1 signal is different for all 3 of: ADD, LW, & SW? RegDst or ExtOp? • “Don’t Care” signals are useful because we can simplify our PLA personality matrix. F / T? ABC 1: SRF 2: SRT 3: SEF 4: SET 5: BRF 6: BRT 7: BEF 8: BET

  18. Datapath And in Conclusion… Single cycle control • 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic • Control is the hard part • MIPS makes that easier • Instructions same size • Source registers always in same place • Immediates same size, location • Operations always on registers/immediates Processor Input Control Memory Output

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