Lecture 16: RISC Architecture, Pipeline Hazards

1. Lecture 16:RISC Architecture, Pipeline Hazards Soon Tee Teoh CS 147

2. Computer Architecture Notes • Stored-program computer • In contrast to fixed-program computer, stored-program computer can load and run different programs easily without any re-design • von Neumann architecture • Single storage structure to hold both program and data • What’s Moore’s Law? • Attributed to Gordon Moore, co-founder of Intel • “The number of transistors on an integrated circuit doubles every 18 months” (although Gordon Moore himself didn’t say 18 months) • Implication: Assume that Moore’s law will be fulfilled, therefore if I am a chip manufacturer, I better perform up to Moore’s law, otherwise I’d probably lose to my competitors. • Another implication: If I am a software developer, I can design my software assuming that computers in the future will be faster

3. RISC or CISC • 2 different types of ISA, different “philosophy”, trade-offs • RISC (Reduced Instruction Set Computers) • CISC (Complex Instruction Set Computers) • RISC: • Memory accesses restricted to load/store, data manipulation are register-to-register • Limited number of addressing modes • All instructions same length • Instructions are elementary • CISC: • Memory access directly available to most instructions • Many different addressing modes • Instructions of varying lengths • Some instructions simple, some complex • Many ISAs are between RISC and CISC

4. Reduced Instruction Set Computer • RISC has elementary, fixed-length instructions, and few addressing modes. • We use an example RISC architecture. • This RISC architecture uses load-store memory access: that is, operations are not performed directly on memory; rather, they are performed only on registers • 32 registers: We need many registers to reduce load/store memory access to temporarily save operands. • The entire instruction set is given in Table 12-1, page 540 • 32-bit instructions. 7-bit opcode field, 5-bit register field, 15-bit immediate field • 2 formats: (1) 3-registers, (2) 2-registers + immediate 7 bits 5 bits 5 bits 5 bits 10 bits 3 registers Opcode DR SA SB 7 bits 5 bits 5 bits 15 bits 2 registers + immediate Opcode DR SA Immediate

5. Addressing Modes • This RISC uses 4 addressing modes: • Register: ADD DR SA SB • Action: R[DR] R[SA] + R[SB] • Register indirect: LD DR SA • Action: R[DR] M[R[SA]] • Immediate: ADI DR SA IM • Action: R[DR] R[SA] + se IM • Relative: BZ DR SA IM • Action: if R[SA] == 0, then PC PC + 1 + se IM

6. Jump and Link • The Jump and Link (JML) instruction allows the programmer to implement procedures • Instruction format: JML DR IM • Action: PC PC + 1 + se IM, R[DR] PC + 1 • JML sets PC to a new value, the address of the callee procedure, and also stores the return address in a register. • When the callee procedure returns, use the Jump Register (JMR) instruction • Instruction format: JMR SA • Action: PC R[SA] • When the callee returns, use the JMR instruction with the register that stored the return address of the caller. • For nested procedure calls, need to use software stack.

7. BrA: The branch address RAA: The jump address Z: If zero (from Function Unit) BS, PS: Flags for branch/jump instructions BS1 BS0 . (BS1 + (PS + Z)) MUX C 0 1 3 2 BrA RAA EX IR DOF EX PC Address From Figure 11-8, page 558, except we ignore the SLT instruction Instruction Memory +1 Instruction PC-1 IR Constant Unit SH BA AA Register File Instruction Decoder CS PC-1 MA MB AA BA CS MA 1 0 MUX A 1 0 MUX B MB MA: Select PC or Register A for functional unit MB: Select Constant or Register B AA, BA: Select which registers to read CS: Sign extend or zero fill the constant PC-2 Address RAA Data Memory BS PS MW FS SH A B Function Unit F SH FS Data out Data in Adder SH: Shift amount for barrel shifter FS: Which function MW: Memory write enable RW: Write to register file DA: Select which register to write MD: Memory of function unit Z Data Memory Address BrA MW RW DA 0 1 MUX D MD Register File RW DA MD

8. Pipeline Hazards • A pipeline hazard prevents the next instruction in the instruction stream from being executing during its designated clock cycle. • Two kinds: • Data hazard • Control hazard

9. Data Hazard Example: MOVA R1, R5 ADD R2, R1, R6 1 2 3 4 5 MOVA R1, R5 IF DOF EX WB ADD R2, R1, R6 IF DOF EX WB At cycle 3, the ADD instruction needs to read the value of R1, but R1 is only available in cycle 4. (Assume that registers are written in the first half of the clock cycle and read in the second half of the clock cycle.) We have a data hazard!

10. How to Deal with Data Hazard • 3 options • Compiler detects data hazard and inserts NOP (no-op, or non-operation, an instruction that does nothing) • Hardware detects data hazard and delays execution of instruction • Hardware implements data forwarding to eliminate data hazard

11. Hardware Detect Data Hazard • Once hazard is detected, hardware inserts NOPs automatically. This is illustrated with bubbles in the pipeline picture. MOVA R1, R5 ADD R2, R1, R6 1 2 3 4 5 MOVA R1, R5 IF DOF EX WB ADD R2, R1, R6 IF DOF ADD R2, R1, R6 IF DOF EX WB Disabled instruction repeated next cycle Hazard detected NOPs inserted to disable pipeline

12. How to Detect Data Hazard Data hazard detected DHS = HA + HB HA = MADOF . (DAEX == AADOF) . RWEX HB = MBDOF . (DAEX == BADOF) . RWEX Instruction in DOF stage takes operand from register Instruction in EX stage writes to register Destination register in EX stage is equal to read register in DOF stage

13. BS1 BS0 . (BS1 + (PS + Z)) MUX C 0 1 3 2 Detecting data hazard, from Figure 11-12, page 566 BrA RAA EX IR DOF EX PC Address Instruction Memory +1 Instruction PC-1 IR Constant Unit SH BA AA Register File Instruction Decoder CS PC-1 MA MB AA BA CS MA 1 0 MUX A 1 0 MUX B MB PC-2 Address RAA Data Memory A B Function Unit F SH FS = Data out HA Data in Adder Z Data Memory Address BrA = DHS MW HB Circuitry for DHS RW DA 0 1 MUX D MD Register File RW DA MD

14. Data Hazard Stall • Assume registers have technology to write in the first half of clock cycle and read in second half of clock cycle. • Therefore, only need to stall for one clock cycle when there is data hazard.

15. Data hazard stall, from Figure 11-12, page 566 Set RW, MW to 0 in the DOF stage to prevent write. Set BS to 0 in the DOF stage to prevent branch. Set DA to 0 in the DOF stage to prevent infinite stall. Disable all the PC registers. BS1 BS0 . (BS1 + (PS + Z)) MUX C 0 1 3 2 BrA RAA EX IR DOF EX PC Address Instruction Memory +1 Instruction PC-1 IR Constant Unit SH BA AA Register File Instruction Decoder CS PC-1 MA MB AA BA CS MA 1 0 MUX A 1 0 MUX B MB Set RW, DA, BS and MW to 0 PC-2 Address RAA Data Memory BS A B Function Unit F SH FS = Data out HA Data in Adder Z Data Memory DHS Address BrA = DHS HB MW Circuitry for DHS RW DA 0 1 MUX D MD Register File RW DA MD

16. BS1 BS0 . (BS1 + (PS + Z)) MUX C 0 1 3 2 Data forwarding, from Figure 11-13, page 568, except SLT instruction not implemented Data already available in EX stage, simply load directly into DOF stage BrA RAA EX IR DOF EX PC Address Instruction Memory +1 Instruction PC-1 IR Constant Unit SH BA AA Register File Instruction Decoder PC-1 CS MA MB AA BA CS HA 2 1 0 MUX A 2 1 0 MUX B HB MA MB PC-2 Address RAA Data Memory A B Function Unit F SH FS = Data out Data in Adder HA Z Data Memory Address MD BrA = MUX D’ MW HB MD RW DA 0 1 MUX D MD Register File RW DA MD

17. Control Hazard • Without any intervention, instructions immediately following branch instructions will be executed regardless of whether branch is taken. This causes error. Example: 1 BZ R1, 18 2 MOV R2, R3 3 MOV R1, R2 Suppose that R1 contains 0, then PC set to 20 1 2 3 4 5 6 BZ R1 18 IF DOF EX WB MOV R2 R3 IF DOF EX WB MOV R1 R2 IF DOF EX WB But these 2 instructions have already been loaded

18. How to Deal with Control Hazard • Insert 2 NOPs after a branch instruction • A smart compiler can rearrange code to try to move 2 instructions into the positions after the branch that should be executed anyway. Usually, these 2 instructions are originally just before the branch instruction. If no such instructions can be found, then the compiler just has to use NOPs.