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數位積體電路雛型製作

數位積體電路雛型製作. Ch07 Verilog 語法的 函數與任務. 內容. 函數與任務 Moore machine mealy machine. 副程式. 函數 (function) 任務 (task) 系統的 使用者自定的. 函數 (function). 解決組合邏輯的轉換與計算， 不能有 delay ，且僅 傳回單一值 ，至少有一輸入。 function [ 位元長度 ] < 名稱 > 參數宣告 ......... 敘述 ; ............. endfunction. 乘 / 除 8 函數範例.

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數位積體電路雛型製作

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  1. 數位積體電路雛型製作 Ch07 Verilog語法的 函數與任務

  2. 內容 • 函數與任務 • Moore machine • mealy machine

  3. 副程式 • 函數(function) • 任務(task) • 系統的 • 使用者自定的

  4. 函數(function) • 解決組合邏輯的轉換與計算，不能有delay，且僅傳回單一值，至少有一輸入。 function [位元長度] <名稱> 參數宣告 .........敘述; ............. endfunction

  5. 乘/除 8函數範例 function [7:0] mult_div_8; input fcn_left; input [7:0] fcn_in; begin mult_div_8 = (fcn_left == 1)? (fcn_in << 3) : (fcn_in >> 3); end endfunction

  6. 3bit左右移當作乘除 module shift_fcn(indata, qout, mout); output [7:0] qout; //quotient output output [7:0] mout; //product output input [7:0] indata; //input data reg [7:0] qout; reg [7:0] mout; //parameter sh_bit = 3; //define the number of bits for shifting parameter left =1; parameter right = 0; always @ (indata) begin mout = mult_div_8(left, indata); // multiplier function call qout = mult_div_8(right,indata); // divider function call end //Function mult_div_8 function [7:0] mult_div_8; input fcn_left; input [7:0] fcn_in; begin mult_div_8 = (fcn_left == 1)? (fcn_in << 3) : (fcn_in >> 3); end endfunction endmodule

  7. 8bit偶同位函數 functioneven8; input [7:0] I8; begin even8 = even4( I8[7:4]) ^ even4(I8[3:0] ); // xor operation end endfunction functioneven4; input [3:0] I4; begin even4 = ^ I4; // reduction xor operation end endfunction

  8. 16bit偶同位函數 module even_parity_16(Din, Pout); input [15:0] Din; output Pout; reg [7:0] High_byte; // Hight byte of input data reg [7:0] Low_byte; // Low byte of input data reg High, Low; // Parities of high and low byte reg Pout; // Parity output always @(Din) begin High_byte = Din[15:8]; Low_byte = Din[7:0]; High = even8(High_byte);//Call function even8 Low = even8(Low_byte); Pout = High ^ Low; //Bitwise xor end function even8; ................................... function even4; ................................... endmodule

  9. 1對2解多工器 function [1:0] DEMUL2; //1 to 2demultiplexer input S; input D; case(S) 1'b0 : DEMUL2 = {1'b0, D}; 1'b1 : DEMUL2 = {D, 1'b0}; default : DEMUL2 = {1'b0, 1'b0}; endcase endfunction

  10. 1對4解多工器 module dmux14_fcn(Din, S, Y); input Din; // Data input input [1:0] S; // 2-bit select line output [3:0] Y; // 4-bit output reg [3:0] Y; reg [1:0] X; always @(Din or S) begin X = DEMUL2(S[1], Din); // The first 1 to 2 demultiplexer Y[1:0] = DEMUL2(S[0], X[0]); // The second 1 to 2 demultiplexer Y[3:2] = DEMUL2(S[0], X[1]); // The third 1 to 2 demultiplexer end function [1:0] DEMUL2; // Function of 1 to 2 demultiplexer ............................... endmodule

  11. 2對4解碼器 function [3:0] decod4; // 4-bit decoder function input [1:0] D; input ce; // Chip enable if (ce == 1'b1) begin case (D) 2'b00 : decod4 = 4'b0001; 2'b01 : decod4 = 4'b0010; 2'b10 : decod4 = 4'b0100; 2'b11 : decod4 = 4'b1000; default : decod4 = 4'b0000; endcase end else decod4 = 4'b0000; endfunction

  12. 3對8解碼器 module decod_fcn(Din, Y); input [2:0] Din; //3-bit data input output [7:0] Y; //8-bit data output reg [7:0] Ytmp; // 8-bit temp register always @(Din) begin Ytmp[7:4] = decod4(Din[1:0], Din[2]); Ytmp[3:0] = decod4(Din[1:0], ~Din[2]); end assign Y = Ytmp; function [3:0] decod4; // 4-bit decoder function ..................................... endmodule

  13. 4 bit 加法器—利用函數 module parallel_adder_4b (Cout, S, x, y, C0); input [3:0] x, y; input C0; output [3:0] S; output Cout; wire C1,C2,C3; // Intermediate carries // Instantiate the full adder assign {C1, S[0]} = full_adder(x[0],y[0],C0); assign {C2, S[1]} = full_adder(x[1],y[1],C1); assign {C3, S[2]} = full_adder(x[2],y[2],C2); assign {Cout, S[3]} = full_adder(x[3],y[3],C3); // Define full-adder function 宣告全加器函數 function [1:0] full_adder; //為2bit 線 input a, b, c0; //參數 begin // The body of function full_adder = a + b + c0; end endfunction endmodule

  14. Task task <名稱> <參數宣告> ................. <敘述區> .................. endtask

  15. 4 bit 加法器—利用task module parallel_adder_4bt (Cout, S, x, y, C0); input [3:0] x, y; input C0; output [3:0] S; output Cout; // Local declaration reg [3:0] S; reg Cout; reg C1,C2,C3; // Intermediate carries // -- 4_bit adder body-- // // Call full-adder task always @(x or y or C0)begin full_adder(C1,S[0],x[0],y[0],C0); full_adder(C2,S[1],x[1],y[1],C1); full_adder(C3,S[2],x[2],y[2],C2); full_adder(Cout,S[3],x[3],y[3],C3); end // Define full-adder task task full_adder; output Co,S; input a, b, c0; // The body of task {Co,S} = a + b + c0; endtask endmodule

  16. 8bit奇同位任務 task odd8; input [7:0] I; output odd8; begin odd8 = ~^ I; // reduction xnoroperation end endtask

  17. 16bit奇同位--任務 module odd_parity_16(Din, Pout); input [15:0] Din; output Pout; reg [7:0] High_byte; // Hight byte of input data reg [7:0] Low_byte; // Low byte of input data reg High, Low; // Parities of high and low byte reg Pout; // Parity output always @(Din) begin High_byte = Din[15:8]; Low_byte = Din[7:0]; odd8(High_byte, High); odd8(Low_byte, Low); Pout = High ~^ Low; // Bitwise xnor end task odd8; .................................... endmodule

  18. 4bit比較器 // Task for a 4-bit comprator task compare4 ; input [3:0] I_A ; //4-bit input I_A and I_B input [3:0] I_B ; output [2:0] S ; //S[2]=1'b1 -->Great than, //S[1]=1'b1 --> Equal, and //S[0]=1'b1 -->Less than begin if( I_A > I_B ) S = 3'b100 ; // Great than else if( I_A == I_B ) S = 3'b010 ; // Equal else S = 3'b001 ; // Less than end endtask

  19. 16bit比較器 module compare16( A, B, Yout ); input [15:0] A ; //16-bit input A and B input [15:0] B ; output [2:0] Yout; //Yout[2]=1'b1 -->Great than, Yout[1]=1'b1 --> Equal, and //Yout[0]=1'b1 -->Less than reg [3:0] A4bit; // 4-bit data in input A reg [3:0] B4bit; // 4-bit data in input B reg [2:0] Yout ; always @( A or B ) begin A4bit = A[15:12] ; B4bit = B[15:12]; compare4( A4bit , B4bit , Yout ); if( Yout == 3'b010 ) // A[15:12] == B[15:12] begin A4bit = A[11:8] ; B4bit = B[11:8] ; compare4( A4bit , B4bit , Yout ) ; if( Yout == 3'b010 ) // A[15:8] == B[15:8] begin A4bit = A[7:4] ; B4bit = B[7:4] ; compare4( A4bit , B4bit , Yout ) ; if( Yout == 3'b010 ) // A[15:4] == B[15:4] begin A4bit = A[3:0] ; B4bit = B[3:0] ; compare4( A4bit , B4bit , Yout ) ; end end end end // Task for a 4-bit comprator task compare4 ; ..................................... endmodule

  20. 限制 • 函數(function)只能呼叫函數，不能呼叫任務(task)

  21. 函數呼叫函數範例

  22. 16bit偶同位產生器 module even_parity_16(Din, Pout); input [15:0] Din; output Pout; reg [7:0] High_byte; // Hight byte of input data reg [7:0] Low_byte; // Low byte of input data reg High, Low; // Parities of high and low byte reg Pout; // Parity output always @(Din) begin High_byte = Din[15:8]; Low_byte = Din[7:0]; High = even8(High_byte); //Call function even8 Low = even8(Low_byte); Pout = High ^ Low; //Bitwise xor end function even8; input [7:0] I8; begin even8 = even4(I8[7:4]) ^ even4(I8[3:0]); // xor operation end endfunction function even4; input [3:0] I4; begin even4 = ^ I4; // reduction xor operation end endfunction

  23. Moore Machine-1

  24. Moore Machine-2 //----------------------------------------------- //Moore machine with Binary encoded state machine //Filename : MOORE_BIN1.v //----------------------------------------------- module MOORE_BIN1(CLK, Din, RESET, Qout); input CLK, RESET; input Din; output Qout; reg Qout; //Declare the value for all states parameter [1:0] S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; //Declare current state and next state variables reg [1:0] CS; reg [1:0] NS;

  25. Moore Machine-3 always @ (posedge CLK or posedge RESET) begin if (RESET == 1'b1) CS = S0; //Initial state else CS = NS; end

  26. Moore Machine-4 always @ (CS or Din) begin case (CS) S0 : begin Qout = 1'b0; if (Din == 1'b0) NS = S0; else NS = S2; end S1 : begin Qout = 1'b1; if (Din == 1'b0) NS = S0; else NS = S2; end S2 : begin Qout = 1'b1; if (Din == 1'b0) NS = S2; else NS = S3; end S3 : begin Qout = 1'b0; if (Din == 1'b0) NS = S3; else NS = S1; end endcase end endmodule

  27. one_hot encoded-1 module MOORE_ONEH1(CLK, Din, RESET, Qout); input CLK, RESET; input Din; output Qout; reg Qout; //Declare the value for all states parameter [3:0] S0 = 4'b0001, S1 = 4'b0010, S2 = 4'b0100, S3 = 4'b1000; //Declare current state and next state variables reg [3:0] CS; reg [3:0] NS;

  28. one_hot encoded-2 always @ (posedge CLK or posedge RESET) begin if (RESET == 1'b1) CS = S0; //Initial state else CS = NS; end

  29. one_hot encoded-3 always @ (CS or Din) begin case (CS) S0 : begin Qout = 1'b0; if (Din == 1'b0) NS = S0; else NS = S2; end S1 : begin Qout = 1'b1; if (Din == 1'b0) NS = S0; else NS = S2; end S2 : begin Qout = 1'b1; if (Din == 1'b0) NS = S2; else NS = S3; end S3 : begin Qout = 1'b0; if (Din == 1'b0) NS = S3; else NS = S1; end endcase end endmodule

  30. 奇同位檢查器-1

  31. 奇同位檢查器-2 module MOORE_BIN2(CLK, Din, RESET, Qout); input CLK, RESET; input Din; output Qout; reg Qout; //Declare the value for all states parameter S0 = 1'b0, S1 = 1'b1; //Declare current state and next state variables reg CS; reg NS;

  32. 奇同位檢查器-3 always @ (posedge CLK or posedge RESET) begin if (RESET == 1'b1) CS = S0; //Initial state else CS = NS; end

  33. 奇同位檢查器-4 always @ (CS or Din) begin case (CS) S0 : begin Qout = 1'b0; if (Din == 1'b0) NS = S0; else NS = S1; end S1 : begin Qout = 1'b1; if (Din == 1'b0) NS = S1; else NS = S0; end endcase end endmodule

  34. 連續2個0奇同位檢查器-1

  35. 連續2個0奇同位檢查器-2

  36. 認識101Mealy machine-1

  37. 認識101-2 module MEALY_GRY1(CLK, Din, RESET, Qout); input CLK, RESET; input Din; output Qout; reg Qout; //Declare the value for all states parameter [1:0] S0 = 2'b00, S1 = 2'b01, S2 = 2'b11; //Declare current state and next state variables reg [1:0] CS; reg [1:0] NS; always @ (posedge CLK or posedge RESET) begin if (RESET == 1'b1) CS = S0; //Initial state else CS = NS; end

  38. 認識101-3 always @ (CS or Din) begin case (CS) S0 : begin if (Din == 1'b0) begin NS = S0; Qout = 1'b0; end else begin NS = S1; Qout = 1'b0; end end S1 : begin if (Din == 1'b0) begin NS = S2; Qout = 1'b0; end else begin NS = S1; Qout = 1'b0; end end S2 : begin if (Din == 1'b0) begin NS = S0; Qout = 1'b0; end else begin NS = S1; Qout = 1'b1; end end endcase end endmodule

  39. 0101序列偵測器-1

  40. 0101序列偵測器-2 module MEALY_GRY2(CLK, Din, RESET, Qout); input CLK, RESET; input Din; output Qout; reg Qout; //Declare the value for all states parameter [1:0] S0 = 2'b00, S1 = 2'b01, S2 = 2'b11, S3 = 2'b10; //Declare current state and next state variables reg [1:0] CS; reg [1:0] NS; always @ (posedge CLK or posedge RESET) begin if (RESET == 1'b1) CS = S0; //Initial state else CS = NS; end

  41. 0101序列偵測器-3 always @ (CS or Din) begin case (CS) S0 : begin if (Din == 1'b0) begin NS = S1; Qout = 1'b0; end else begin NS = S0; Qout = 1'b0; end end S1 : begin if (Din == 1'b0) begin NS = S1; Qout = 1'b0; end else begin NS = S2; Qout = 1'b0; end end

  42. 0101序列偵測器-4 S2 : begin if (Din == 1'b0) begin NS = S3; Qout = 1'b0; end else begin NS = S0; Qout = 1'b0; end end S3 : begin if (Din == 1'b0) begin NS = S1; Qout = 1'b0; end else begin NS = S2; Qout = 1'b1; end end endcase end endmodule

  43. 0101及1001序列偵測器-1

  44. 0101及1001序列偵測器-2 module MEALY_GRY3(CLK, Din, RESET, Qout); input CLK, RESET; input Din; output Qout; reg Qout; //Declare the value for all states parameter [2:0] S0 = 3'b000, S1 = 3'b001, S2 = 3'b011, S3 = 3'b010, S4 = 3'b110, S5 = 3'b111, S6 = 3'b101; //Declare current state and next state variables reg [2:0] CS; reg [2:0] NS; always @ (posedge CLK or posedge RESET) begin if (RESET == 1'b1) CS = S0; //Initial state else CS = NS; end

  45. 0101及1001序列偵測器-3 always @ (CS or Din) begin case (CS) S0 : begin if (Din == 1'b0) begin NS = S1; Qout = 1'b0; end else begin NS = S2; Qout = 1'b0; end end S1 : begin if (Din == 1'b0) begin NS = S5; Qout = 1'b0; end else begin NS = S3; out = 1'b0; end end

  46. 0101及1001序列偵測器-4 S2 : begin if (Din == 1'b0) begin NS = S3; Qout = 1'b0; end else begin NS = S5; Qout = 1'b0; end end S3 : begin if (Din == 1'b0) begin NS = S4; Qout = 1'b0; end else begin NS = S6; Qout = 1'b0; end end

  47. 0101及1001序列偵測器-5 S4 : begin if (Din == 1'b0) begin NS = S0; Qout = 1'b0; end else begin NS = S0; Qout = 1'b1; end end S5 : begin if (Din == 1'b0) begin NS = S6; Qout = 1'b0; end else begin NS = S6; Qout = 1'b0; end end S6 : begin if (Din == 1'b0) begin NS = S0; Qout = 1'b0; end else begin NS = S0; Qout = 1'b0; end end endcase end endmodule

  48. 3bit偶同位產生器-1

  49. 3bit偶同位產生器-2 module MEALY_BIN1(CLK, Din, RESET, Qout); input CLK, RESET; input Din; output Qout; reg Qout; //Declare the value for all states parameter [2:0] S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101, S6 = 3'b110; //Declare current state and next state variables reg [2:0] CS; reg [2:0] NS; always @ (posedge CLK or posedge RESET) begin if (RESET == 1'b1) CS = S0; //Initial state else CS = NS; end

  50. 3bit偶同位產生器-3 always @ (CS or Din) begin case (CS) S0 : begin if (Din == 1'b0) begin NS = S1; Qout = 1'b0; end else begin NS = S2; Qout = 1'b0; end end S1 : begin if (Din == 1'b0) begin NS = S3; Qout = 1'b0; end else begin NS = S4; Qout = 1'b0; end end

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