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Maciej Ciesielski Electrical & Computer Engineering University of Massachusetts, Amherst, USA

Taylor Expansion Diagrams: A Compact Canonical Representation for Symbolic Verification and Synthesis. Maciej Ciesielski Electrical & Computer Engineering University of Massachusetts, Amherst, USA ciesiel@ecs.umass.edu . B. A. A. F 1. +. *. F 2. -. 1 0. *. 0 1. B. -. a k. s 1.

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Maciej Ciesielski Electrical & Computer Engineering University of Massachusetts, Amherst, USA

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  1. Taylor Expansion Diagrams:A Compact Canonical Representationfor Symbolic Verification and Synthesis Maciej Ciesielski Electrical & Computer Engineering University of Massachusetts, Amherst, USA ciesiel@ecs.umass.edu Taylor Expansion Diagrams

  2. B A A F1 + * F2 - 1 0 * 0 1 B - ak s1 D * D s2 ak bk > bk Motivation – RTL Verification • Check equivalence of two RTL designs • Complex RTL designs: • data flow and • control • Interaction • Arithmetic and Boolean • Data flow and control Taylor Expansion Diagrams

  3. Common Representations • Boolean functions ( f : B  B ) • Truth table, Karnaugh map • SoP, PoS, ESoP • Reed-Muller expansions (XOR-based) • Decision diagrams (BDD, ZDD, etc.) • Arithmetic functions ( f : B  Int ) • Binary Moment Diagrams (*BMD, K*BMD, *PHDD) • Multi-terminal, Algebraic Decision Diagrams (ADD) • Arithmetic functions (f : Int  Int ) • Taylor Expansion Diagrams (TED) Taylor Expansion Diagrams

  4. Canonical Representations • Each minimal, canonical representation is characterized by • Decomposition type • Shannon, Davio, moment decomposition, Taylor exp., etc. • Reduction rules • Redundant nodes, isomorphic sub-graphs, etc. • Composition method (“Apply”, composition rule) • What they represent • Boolean functions (f : B  B) • Arithmetic functions (f : B  Int ) • Algebraic expressions (f : Int Int ) Taylor Expansion Diagrams

  5. Decomposition Types • Shannon expansion f = x fx + x’ fx’ • Moment decomposition: replacex’=1-x f = x fx + (1-x) fx’ = fx’ + x fx where fx = fx - fx’ • also called positive Davio decomposition Taylor Expansion Diagrams

  6. Binary Decision Diagrams (BDD) • Based on recursive Shannon expansion f = x fx + x’ fx’ • Compact data structure for Boolean logic • can represents sets of objects (states) encoded as Boolean functions • Canonical representation • reduced ordered BDDs (ROBDD) are canonical • essential for verification Taylor Expansion Diagrams

  7. Binary Moment Diagrams (*BMD) • Devised for word-level operations, arithmetic • Based on modified Shannon expansion (positive Davio) f = x fx + x’ fx’ = x fx + (1-x) fx’ = fx’ + x (fx - fx’ ) = fx’ + x fx where fx’ = fx=0,is zero moment fx = (fx - fx’ )is first moment • Additive and multiplicative weights on edges (*BMD) Taylor Expansion Diagrams

  8. x3 x2 x1 x0 8 4 0 8 4 2 1 1 0 x0 x1 x2 x3 2 1 *BMD - Construction • Unsigned integer: X = 8x3 + 4x2 + 2x1 + x0 • X(x3=1) = 8 + 4x2 + 2x1 + x0 • X(x3=0) = 4x2 + 2x1 + x0 • Xx3 = 8 *BMD BMD Multiplicative edges Taylor Expansion Diagrams

  9. 4 2 4 1 2 1 4 4 0 0 1 1 x1 x2 x0 x0 x1 x2 y2 y1 y0 y2 y1 y0 2 2 1 1 Word level Word level *BMD - Word Level Representation • Efficiently modeling symbolic word-level operators X Y X+Y Taylor Expansion Diagrams

  10. Properties of BDDs and *BMDs • Both are canonical for fixed variable order • BDDs • Good for equivalence checking and SAT • Inefficient for large arithmetic circuits (multipliers) • BMDs • Efficient for word-level operators • Less compact for Boolean logic than BDDs • Good for equivalence checking, but not for SAT • Insufficient for high-order arithmetic expressions Taylor Expansion Diagrams

  11. X Y X + Y 0 0 1 1 X Y X Y Symbolic level Symbolic level Symbolic Level Representation • Can we devise a truly symbolic representation? • more general representation than “word-level” *BMD Taylor Expansion Diagrams

  12. F(x) x … F1(x) F0(x) F2(x) Taylor Expansion Diagram (TED) • Let F be a continuous, differentiable function • Taylor Expansion (around x=0): F(x) = F(0) + x F’(0) + ½ x2 F’’(0) + … • Notation • F0(x) = F(x=0) 0-child - - - - - - • F1(x) = F’(x=0) 1-child---------- • F2(x) = ½ F’’(x=0) 2-child====== • etc. F(x) = F0(x)+ x F1(x) + x2 F2(x) + … Taylor Expansion Diagrams

  13. F0(A) =F|A=0 = 2C + 3 F1(A) =F’|A=0 = 2AB|A=0 = 0 C A B C A B F2(A) =½ F’’|A=0 = B H0(B) =B|B=0 = 0 H1(B) =B’= 1 0 2 3 1 G0(C) = (2C+3)|C=0 = 3 G1(C) = (2C+3)’= 2 Construction - Your First TED F = A2B + 2C + 3 H G= 2C + 3 (before normalization) *BMD : requires bit-level expansion! Taylor Expansion Diagrams

  14. *BMD requires bit-level expansion works on bit level modeled with constant and first moment only 8 0 1 2 x0 x1 x2 x1 x0 x0 4 TED vs *BMD • *BMD representation of F = X2, X={x2, x1, x0} F = (4x2 + 2x1 + x0)2 = 16x2+ 16x2x1+ 8x2x0+4x1+ 4x1x0+ x0 Taylor Expansion Diagrams

  15. (A+B)(A+2C) (A+B)C +1 64 A B A B 16 16 B 8 4 4 1 2 C C 4 1 1 0 1 0 1 0 1 1 1 1 x1 x0 x0 x1 x3 x2 x2 2 1 1 1 TED – a few Examples Taylor Expansion Diagrams

  16. a) Nodes with all empty edges f f a a g g 0 0 0 b b TED Reduction Rules # 1 • Eliminate redundant nodes: b) with only a constant term f = 0 a2 + 0 a + g(b) = g(b), independent of a f = 0 a2 + 0 a + 0 = 0 Taylor Expansion Diagrams

  17. 2. Merge isomorphic subgraphs (identical nodes) A A 1 6 6 5 5 1 B B B B 1 1 0 1 0 0 1 C C C C TED Reduction Rules # 2 (A2 + 5A + 6)(B + C) Taylor Expansion Diagrams

  18. B A B A 2 6 1 2 2 A 2 2 B 1 1 1 3 3 1 TED Normalization • TED is normalized if • there are no more than two terminalnodes: 0 and 1 • weights of edges of a given node must be relativelyprime (to allow sharing isomorphic graphs) 2(A + B + 3) 2A + 2B + 6 normalized Taylor Expansion Diagrams

  19. A A A 1 6 6 5 5 1 B B B B B B B 1 5 0 0 1 6 0 1 0 1 1 0 C C C C C C C Normalization - Example (A2 + 5A + 6)(B + C) Taylor Expansion Diagrams

  20. h = f OP g z OP OP= (+, - , •) f g u x y q v TED: Composition • Recursive composition of nodes, starting at the top • Operation depends on relative order of variables x, y • if x = y, then z = x, and h(x) = f(x) OP g(x) = f0(x) OP g0(y) + x [f1(x) OP g1(y)] + x2[f2(x) OP g2], … • if x > y, then z = x, and h(x) = f0(x) + g(y) + x f1(x) + x2f2(x) + … (for OP = +) h(x) = f0(x) • g(y) + x [f1(x) • g(y)] + x2[f2(x) • g(y)] … (for OP =•) = Taylor Expansion Diagrams

  21. x x x u v u + v u0+v0 u1+v1 u0 u1 v0 v1 x y x u u + v v u0+ v u0 u1 v0 v1 u1 COMPOSE Operator – ADD/SUB • Nodes indexed by same variable = + • Nodes indexed by different variable (x > y) = + Taylor Expansion Diagrams

  22. x x x u • v u v u1•v1 u0•v0 u0 u1 v0 v1 u0•v1+u1•v0 x y u x u • v v u0 u1 v0 v1 u0 • v u1 • v COMPOSE Operator – MULT • Nodes indexed by same variable = • • Nodes indexed by different variable (x > y) = • Taylor Expansion Diagrams

  23. A+B A+2C A A A B B C 4 6 C 1•5 1•5 0+7 4•6 3•5 3•1 0•5 3 8 7 5 A 1 1 1 2 2 1 0 0 0 2 0 0 0•2 1•2 1•2 1•1 0•1 0•0 1•0 1•1 1•0 1 B B B B C C 8+7 C 2 0+2 0+0 COMPOSE Operation - Example B = + * C (A+B)(A+2C) + = Taylor Expansion Diagrams

  24. Canonical Compact Linear for polynomials of arbitrary degree TED for Xk, k = const, with n bits, hask(n-1)+1 nodes. Can contain symbolic, word-level, and Boolean variables It is not a Decision Diagram X2=(8x3+4x2+2x1+x0)2 64 16 16 8 4 4 4 1 1 1 1 0 1 x1 x0 x1 x0 x3 x2 x2 2 1 1 1 Properties of TED n = 4, k = 2 Taylor Expansion Diagrams

  25. x x x x x y = x y x  y = (x + y – x y) x  y = (x + y – 2 x y) x’ = (1-x) 1 -1 y y y y y 0 0 0 0 1 1 1 1 -1 -2 1 1 NOT XOR AND OR TED for Boolean logic • Needed to model arithmetic-Boolean interface • Same as *BMD for Boolean logic Taylor Expansion Diagrams

  26. B + A F1 Ahi Alo 1 0 * - Ahi ak s1 D > bk 2(k+1) ak 2k Alo s1 = ak (1-bk) 1 0 TED for Arithmetic Circuits • Arithmetic circuits contain related word-level (A, B) and Boolean (ak, bk) variables A = [ an-1, …, ak , …,a0 ] = 2(k+1)Ahi + 2k ak + Alo Taylor Expansion Diagrams

  27. B A + * F2 A F1 - 1 0 * 0 1 B - * D s2 ak s1 ak D > bk bk Applications to RTL Verification • Equivalence checking with TEDs • interacting word-level and Boolean variables A = [an-1, …,ak,…,a0] = [Ahi,ak,Alo], B = [bn-1, …,bk,…,b0] = [Bhi,bk,Blo] F2 = (1-s2) (A2-B2) + s2 D s2 = ak’ bk = 1 - ak + ak bk F1 = s1(A+B)(A-B) + (1-s1)D s1 = (ak > bk) = ak (1-bk) Taylor Expansion Diagrams

  28. B F1 = F2 + A F1 1 0 * - ak s1 1 D > bk 1 -1 -1 A * F2 - 0 1 22k+2 B * 2k+2 D s2 Ahi Alo Blo ak -22k+2 ak bk bk ak 1 0 0 1 D -2k+2 ^2 ^2 bk Bhi 2k 2k = power edge RTL Equivalence Checking Taylor Expansion Diagrams

  29. A0 A1 FFT(A) A2 FAB1 IFFT0 A3 IFFT1 FAB2 InvFFT(FAB) IFFT2 FAB2 B0 IFFT3 FAB3 B1 FFT(B) B2 B3 x x x x C0 A[0:3] C1 Conv(A,B) C2 B[0:3] C3 Verification of Algorithmic Specifications Taylor Expansion Diagrams

  30. IFFT0 = C0 A0 A2 A1 A3 B0 • B2 B3 B1 4 0 Equivalence: Checking for TED Isomorphism 4{ A0*B0 + A1*B3 + A2*B2 + A3*B1} In general, this proves: IFFT(i) Conv(i) Taylor Expansion Diagrams

  31. X X 0  4   3 = X X = Y   4 3 Y = * Y Y   2 1     0 4 2 3 1 0 1  3  1 + = 0 1 1 0 0 Complex and GF Computations • Works for complex values and Galois Field (GF) operators • Assume Galois Field GF[8], let 0 be primitive • element of GF(8) • Q[XY] = (4 X + 2 Y)(3 X + 1 Y) • R[XY] = 0 X + 3 Y • Q and R are equivalent, have isomorphic TEDs Taylor Expansion Diagrams

  32. Cout B + A Sum Limitations of TED Representation • Non-linear design blocks (comparators, etc) • Cannot be represented as polynomials in Integer domain • Require decomposition at bit level • Complexity comparable to BDD’s • Partial expansion of vectors (bit select) • Example: carry-out in adders, sign bit, etc A, B, Sum – word level variables Taylor Expansion Diagrams

  33. Z=A+B A + B F(Z,B[4:3]) G(A, BHI, B[4:3], BLO) B[4:3] A + Z = A+B B A Z=A+B + B Z[4:3] Limitation: Internal Partial Fanout • Computations w/outinternal partial fanouts: “nice” polynomials • Internal partial fanouts: problem • Cannot represent subvectors as continuous functions (polynomials), cannot model them as TED Taylor Expansion Diagrams

  34. Z[n] = F1(A,B) Z=A+B A + Z[..] = F2(A,B) B Z[k:l] = F3(A,B) Z[k:l] Modeling Multiple-Output Discrete Functions • Consider the output sub-vectors as individual functions • - Discrete functions, arbitrary ? • Problem: can we model these discrete functions as polynomials in terms of input symbolic variables, without going down to bit level ? • We recently attempted to model those signals as characteristic polynomials in GF, based on GF decomposition • Problem: high order polynomials (2k for k bits) Taylor Expansion Diagrams

  35. Modeling Discrete Functions in GF(N) Based on decomposition in GF(N) [Pradhan’78] • Consider a multi-valued variable A, integer  [0,…,N] • Let Ak = 1 if A = k, and Ak = 0 otherwise • For two-input function F(A,B) a term Ak Bican be written as • Ak Bi= [1 – (A – k)N] [1 – (B – i)N] • For example, in GF(N=4): • A1 Bα = [1 – (A – 1)3] • [1 – (B – α)3] = 1 if and only if A=1 and B=α • For all other values of A, B, this term = 0 • This is a property of GF(N) Taylor Expansion Diagrams

  36. Conclusions • Features of TED • Canonical • Compact • Represents arithmetic (word-level) blocks + Boolean logic • Applications • Symbolic simulation (representation) • Equivalence checking, RTL verification • Algorithm verification • Varied computational domains: integer, binary, complex, GF, etc. • DSP, error correction coding, cryptography…. • Other potential applications Taylor Expansion Diagrams

  37. Discussion • Limitations • Increase in Boolean logic increases TED complexity • Problem: internal fanouts and multiple-output functions • Cannot break outputs into sub-vectors • Functions cannot be modeled as low order polynomials • Open problems • Satisfiability, functional test generation • Finite precision arithmetic Taylor Expansion Diagrams

  38. Taylor Expansion Diagrams Application to Behavioral Synthesis Taylor Expansion Diagrams

  39. Specification (HDL) Data Flow Graph Area Power Latency Objectives, constraints: ... Architectural solution minimized for given objective, constraints Architecture High Level Synthesis Taylor Expansion Diagrams

  40. A B A C A C Cycle 1 + x x x + x A B Cycle 1 Cycle 2 Cycle 2 Cycle 3 F F Architecture 1: 2 Mult, 1 Add, L = 2 cycles Architecture 2: 1 Mult, 1 Add, L = 3 cycles High Level Synthesis Example Inputs: A, B, C, D Output: F ……… assign F = A*B + A*C ………. Single Data Flow Graph (DFG) Taylor Expansion Diagrams

  41. x x x + x + x + x Latency Area A C A B A C Cycle 1 Cycle 1 A B Cycle 2 Cycle 2 Cycle 3 High Level Synthesis - current F = A*B + A*C Specification • Algorithms: • Scheduling • Allocation • Resource binding Single data flow graph Taylor Expansion Diagrams

  42. B C + x Cycle 1 A Cycle 2 F Alternative architecture: 1 Mult, 1 Add, L = 2 cycles Alternative solution • To derive alternative solutions, need different Data Flow Graph • user must rewrite the initial specification (HDL) • replace (A B + A C) by A (B + C) • The data flows are derived directly from user’s specification • There is a need for a higher level of synthesis: • Transformation A*B + A*C = A*(B+C) • Abstract level synthesis should provide • Canonical representation • Basis for optimal solutions for different objectives Taylor Expansion Diagrams

  43. Current HL Transformation Methods • Ad-hoc methods (algebraic) • Commutativity:A + B = B + A • Associativity:A + (B +C) = (A + B) + C • Distributivity:A * (B +C) = (A * B) + (A * C) • Term rewriting, etc. • Tools • Matlab, Maple • Mathematica • Problems: • not canonical • cannot scale with design size • require manual intervention Taylor Expansion Diagrams

  44. HLD F = AB + AC A A B C A B C B +   C  + 0 1 F2 = A (B + C) F1 = AB + AC TEDs for Behavioral Synthesis • Given an algorithm, derive several implementations using common (canonical) structure of TED Taylor Expansion Diagrams

  45. + x + x B C Cycle 1 A Cycle 2 Alternative Architecture F = A*(B+C) Specification Data flow graph Area Taylor Expansion Diagrams

  46. Current and Future Work • Current work • Interface with GAUT (architectural synthesis system) • Behavioral VHDL front-end • TEDs automatically generated from behavioral descriptions • TED ordering (static, dynamic) • Future work • Fully integrate with GAUT system • Derive TED from behavioral input • Decompose TED guided by some objective: • generate best DFG for given objective (patent pending) • Interface with SystemC (Univ. Bremen?) • Open problems • Satisfiability, functional test generation • Finite precision arithmetic Taylor Expansion Diagrams

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