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csda. csda. XP 2 : A New Compact Representation for Manipulating Arithmetic Circuits. Ajay K. Verma, Philip Brisk and Paolo Ienne Processor Architecture Laboratory (LAP) & Centre for Advanced Digital Systems (CSDA) Ecole Polytechnique Fédérale de Lausanne (EPFL).
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csda csda XP2: A New Compact Representation for Manipulating Arithmetic Circuits Ajay K. Verma, Philip Brisk and Paolo Ienne Processor Architecture Laboratory (LAP) & Centre for Advanced Digital Systems (CSDA) Ecole Polytechnique Fédérale de Lausanne (EPFL)
Logic Synthesis For Arithmetic Cicruits • Sum-of-Product (SoP) and Product-of-Sum (POS) Form • Well-studied (e.g., Espresso), but… • Arithmetic circuits are XOR-dominated • Reed-Muller Form (XOR of Products) • In principle, good for arithmetic circuits, but… • Exponential growth in size compared to POS/SUM • Parallel counter • Leading Zero Anticipator (LZA) • Arithmetic circuits with control logic at the periphery. • Contribution: • XP2: A Reed-Muller alternative without the exponential blowup
Motivational Example z0 = Maj (a1, a3, a5, a7, a9, a11, a13) z1 = Maj (a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14) 0.35 ns 705 μm2 0.74 ns 2200 μm2 0.75 ns 2275 μm2 0.75 ns 2815 μm2 0.79 ns 16397.2 μm2 Synthesis from SoP Form:
Outline • Related work • XP2: a new compact representation • Superiority over other representations • Results from abstract algebra • Null spaces and their use in factorization • Minimization algorithm for XP2 representation • Iterative split-merge approach • Manipulation algorithms (CSE elimination) • Results • Conclusions and future work
Related Work • General circuits • SOP/POS Form • Minimisation (e.g., Espresso) [Brayton84] • Factored form [Brayton82, Brayton87] • Binary Decision Diagram [Lee59] • Minimisation algorithm by partitioning [Yang02] • Representation of XOR-dominated circuits • Generalized Reed-Muller form [Sasao90] • Manipulation algorithms [Verma06, Verma07] • 2-SPP form [Bernasconi06] • Three-level Boolean expressions [Ishikawa04]
Sum of Products and Reed-Muller Form • SP1 = SP – SOP Form • SPk – Sum of products of SPk-1 expressions • The SPk representation of the XOR of n variables is exponentially large for any constant k. • Theorem 2. The Reed-Muller expansion of the OR of n variables is exponentially large. • The n-bit parity function is exponentially large in any SPkrepresentation [Furst84]
XP2 Form XP: Generalized Reed-Muller expression PXP: Product of XP expressions XP2: XOR of PXP expressions XPk: XOR of PXPk-1expressions
f = ab + pqr + ac + xyr f = 1 (1 ab) (1 pqr) (1 ac) (1 xyr) f = (a + x) (p + y + r) (b + c) (a + r) f = (1 a x) (1 p y r) (1 b c) (1 a r) Why XP2? • Theorem 3. If the SoP/PoS representation of a circuit has size k, then the size of the XP2 representation is O(k) • Linear growth! • Reed-Muller Form grows exponentially in k SOP XP2 POS XP2
(p q) (p q) (c d) x (x z pc pd qc qd) (x z) (ay bef) (p q) AND AND AND AND Optimizing XP2 Expressions 1. Factorize 3. Merge 2. Split (ay bef) ((ay bef)(c d) x) (acy ady bcef bdef x) Not a Generalized Reed-Muller Form Expression! AND XOR
CSE Elimination in XP2 Representation find_CSE (expr E1, expr E2) { Introduce new variables λ and μ; E = λE1μE2; minimize (E); S = set of PXP’s which have a product term of the form (λX μY); T = {p | p(λX μY) S, for some X, Y}; return T; }
CSE Elimination: An Example E1 = (ab cd) (p q) pq (c d) E2 = (ab pq) (c d) cd (a b) E = λE1μE2 = λ(ab cd) (p q) λpq (c d) μ(ab pq) (c d) μcd (a b) minimization E = pq (c d)(λ μ) ab(λ (p q) μ (c d)) cd(λ (p q) μ (a b)) CSE = {pq (c d), ab, cd}
Experimental Setup Manually designed (CSE) SOP form Input circuit RM and Generalized RM form XP2 form (CSE) XP2 form CSE elimination Performance criteria: Literal Count
Results (1 of 4) Generalized Reed-Muller Form Benchmark SOP form Reed-Muller Form XP2 form (no CSE) XP2 form (CSE) Manually Designed 16-bit LZD 220 1.81 x 106 332 154 66 64 16-bit LOD 220 602 332 154 66 64 16-bit Barrel Shifter 1280 4752 1280 896 288 192 16-bit Adder 5.24 x 106 9.18 x 105 9.18 x 105 1194 237 89 16-bit Comparator 1.05 x 106 4.81 x 108 1.05 x 106 246 85 63 5.19 x 105 5.72 x 104 5.72 x 104 1854 567 77 15:4 Counter 15-bit Majority 5.15 x 104 5.15 x 104 5.15 x 104 1479 543 71 12-bit CSA Large 1.24 x 1012 1.24 x 1012 3336 250 149 16-bit LZA Large Large Large 42602 3136 152 Performance criteria: Literal Count
Results (2 of 4) • SOP/GRM Exponential growth as a function of bitwidth • XP2 Linear growth as a function of bitwidth Adder
Results (3 of 4) • Not XOR-dominated • XP2 has a similar literal count as SoP/GRM Barrel Shifter
Results (4 of 4) Reed-Muller XP2 • Diminishing returns observed as k increases
Conclusions and Future Work • XP2 • XOR-based representation for arithmetic circuits • Avoids exponential size complexity • Logic optimization fundamentals • Factorization • Split • Merge • CSE Elimination • Develop a complete logic synthesis package using XP2
Results from Abstract Algebra: Null Space Factorization • Null space of X, N (X): • All expressions F, which satisfy FX = 0 • ab N (a b) f = (a b) (cd e) (c d) (ab e) f = (a b) (cd e) (c d) (ab e) ab N (a b) f = (a b) (cd ab e) (c d) (ab e) f = (a b) (cd ab e) (c d) (ab e) f = (a b) (cd ab e) (c d) (ab e) cd N (c d) f = (a b) (cd ab e) (c d) (ab cd e) f = (a b) (cd ab e) (c d) (ab cd e) f = (a b) (cd ab e) (c d) (ab cd e) f = (a b c d) (ab cd e) f = (a b c d) (ab cd e)
Relative Compactness of SPk and XPk XPk: XOR of products of XPk-1 expressions SPk (n) = set of Boolean expressions whose representation size in SPk is n XPk (n) = set of Boolean expressions whose representation size in XPk is n
Minimization of XP2 representation Minimize (expr E) { do { Factorize (E) Split (E); Merge (E); } while (there is a reduction in size) output E; } Accepting only smaller expressions might cause sub-optimality
