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Instruction Level Parallelism ILP

PRESENTED BY: SUNIL KUMAR SAHU B B M TRIPATHI ANISH ANURAG. Instruction Level Parallelism ILP. Sequential execution ILP execution Comparison of Seq. execution vs. ILP execution Dependence Data dependence Types of data hazard Techniques to avoid Control Dependence

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Instruction Level Parallelism ILP

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  1. PRESENTED BY: SUNIL KUMAR SAHU B B M TRIPATHI ANISH ANURAG Instruction Level Parallelism ILP

  2. Sequential execution • ILP execution • Comparison of Seq. execution vs. ILP execution • Dependence • Data dependence • Types of data hazard • Techniques to avoid • Control Dependence • Techniques to avoid • Structure Dependence • Techniques to avoid • Name Dependence • Techniques to avoid Outline

  3. Instructions Execution is Stage wise Utilization of Hardware = 1/4 Sequential Execution

  4. ILP Execution

  5. Sequential execution (Without ILP) Add r1, r2  r8 4 cycles Add r3, r4  r7 4 cycles 8 cycles • ILP execution (overlap execution) Add r1, r2  r8 Add r3, r4  r7 5 cycle Sequential vs ILP

  6. Suppose we have 100 instruction • Sequential manner we need 400 clock • ILP execution take 103 clock speedup = 400/103 = 3.88 efficiency of pipeline = speedup/stages*100 =3.88/4*100 =97% Example 2

  7. Dependences are a property of programs If two instructions are data dependent they can not execute simultaneously A dependence results in a hazard and the hazard causes a stall Dependences may occur through registers or memory Dependences and Hazards

  8. Data True dependence • Control Dependence • Resource Dependence • Name dependencies Types of Dependencies

  9. Data hazards • There are three situations in which a data dependences can occur • read after write (RAW) • write after read (WAR) • write after write (WAW) • No hazard in RAR dependence

  10. Example i1. R2 <- R1 + R3 i2. R4 <- R2 + R3 Read After Write (RAW)

  11. Example i1. R4 <- R1 + R3 i2. R3 <- R1 + R2 Write After Read (WAR)

  12. Example: i1. R2 <- R4 + R7 i2. R2 <- R1 + R2 Write After Write (WAW)

  13. Operand forwarding • Instruction Rescheduling Techniques to avoid data hazard

  14. A control dependency result due to branch instruction. • Constraints. Control Dependences

  15. Prediction • Static branch prediction • Dynamic branch prediction • Instruction Rescheduling • Static scheduling • Dynamic scheduling • Loop unrolling Techniques to avoid

  16. Occurs due to non-availability of sufficient resources. Resource dependences

  17. Keep sufficient resource. • Otherwise issue new instruction completion of previous one. that is stall will happen. Techniques to avoid

  18. Output dependence • Anti-dependence • Techniques to avoid • Register Renaming Name dependences

  19. Instruction-Level Parallel Processing: History, Overview and Perspective. B. Ramakrishna Rau, Joseph A. Fisher. Journal of Supercomputing, Vol. 7, No. 1, Jan. 1993, pages 9-50. Limits of Control Flow on Parallelism. Monica S. Lam, Robert P. Wilson. 19th ISCA, May 1992, pages 19-21. Global Code Generation for Instruction-Level Parallelism: Trace Scheduling-2. Joseph A. Fisher. Technical Report, HPLabs HPL-93-43, Jun. 1993. ILP open problems http://www.ececs.uc.edu/~ddel/projects/dss/hls_paper/node9.html Computer Architecture A Quantitative Approach, Hennessy & Patterson, 3rd edition, M Kaufmann References

  20. Thanking you Questions ?

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