Thanyapat Sakunkonchak and Masahiro Fujita

1. Verification of Event-Based Synchronization of SpecC Description Using Difference Decision Diagrams Thanyapat Sakunkonchak and Masahiro Fujita Introduction The Verification Problem Boolean Program (BP) Difference Decision Diagrams Verification Flows Conclusion and Outlook • More and more complex and larger VLSI must be designed with shorter time-to-market • SoC needs simultaneous development of both HW and SW • Needs ways to describe HW/SW seamlessly • C-based specification/design languages are promising • SpecC [http://www.SpecC.org] • Standardized for HW/SW co-design • Based on ANSI-C and extended • Given SpecC programs, check if specific ordering of executions are guaranteed or not • Along with well-accepted Boolean comparison techniques for logic designs , this could be a basic verification method to check if sequential and parallel version of the same SpecC are equivalent or not • Proposed by Ball and Rajamani under SLAM project at Microsoft Research • Think of SW like a model (like FSM in HW) and verify it by first abstracting away unnecessary statements with user-defined predicates • BP abstracts the original program: • if properties on BP hold, so as original one • Introduce by MΦller, et al. • Symbolic representation of ‘non-boolean’, such as inequality: less efficient if using BDD • DDD represents difference constraints (x-y≤c), x,y are integers, c is constant • Current implementation: • Can handle basic SpecC constructs only • Able to get some properties to be checked • Verify for Satisfied or Unsatisfied (no error trace): “Don’t know” is don’t know (no support) • Future plan: • When verification fails, try to give the counter-examples (error trace) • Based on error traces, plan to develop automatic “refinement of abstractions” • Expand capability to support more complex SpecC structure, e.g. loop, functions, recursive Represents graph for ¬(x−z<1)Λ(x−y≤0)Λ(y−z≤2)