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Circuitos Lógicos e Organização de Computadores Capítulo 7 – Flip-Flops e Circuitos Seqüenciais

Circuitos Lógicos e Organização de Computadores Capítulo 7 – Flip-Flops e Circuitos Seqüenciais. Ricardo Pannain pannain@puc-campinas.edu.br http://docentes.puc-campinas.edu.br/ceatec/pannain/. Set. Sensor. ¤. On. Off. Memory. Alarm. element. Reset. Circuito Seqüenciais.

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Circuitos Lógicos e Organização de Computadores Capítulo 7 – Flip-Flops e Circuitos Seqüenciais

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  1. Circuitos Lógicos e Organização de ComputadoresCapítulo 7 – Flip-Flops e Circuitos Seqüenciais Ricardo Pannain pannain@puc-campinas.edu.br http://docentes.puc-campinas.edu.br/ceatec/pannain/

  2. Set Sensor ¤ On Off Memory Alarm element Reset Circuito Seqüenciais Circuito combinacional  saídas dependem apenas das entradas Cicuito seqüencial  saídas dependem das entradas e do comportamento anterior do circuito Exemplo - Controle de Sistema de Alarme

  3. Load A B A B Data Output Reset TG1 Set Q TG2 Elemento de memória simples Elemento de memória com portas NOR Elemento de memória controlado

  4. Q S R Q R a b Q a (sem alteração) 0 0 0/11/0 0 1 0 1 1 0 1 0 1 1 0 0 Q b S (a) Circuito (b) Tabela Verdade t t t t t t t t t t 1 2 3 4 5 6 7 8 9 10 1 R 0 1 S 0 1 Q ? a 0 1 Q ? b 0 Time (c) Diagrama de Tempo Latch construído com portas NOR

  5. ( ) Q t + 1 Clk S R ¢ R R Q 0 x x Q( t ) (sem alteração) 1 0 0 Q( t ) (sem alteração) Clk 1 0 1 0 1 1 0 1 Q 1 1 1 x S ¢ S (a) Circuito (b) Tabela Verdade 1 Clk 0 1 R 0 1 S 0 1 ? Q 0 1 ? Q 0 Time (c) Timing diagram Q S Clk R Q (d) Símbolo Gráfico Latch SR com clock (gated)

  6. Latch SR Gated SR com portas NAND S Q Clk Q R

  7. S D (Data) Q Clk Q R (a) Circuito ( ) Clk D Q t + 1 Q D ( ) Q t 0 x 1 0 0 Clk Q 1 1 1 (b) Tabela Verdade (c) Símbolo Gráfico Latch D Gated t t t t 1 2 3 4 Clk D Q Time (d) Diagrama de Tempo

  8. t su t h Clk D Q Setup and hold times Setup time  tempo mínimo que D deve estar estável antes da descida do clock Hold time  temp mínimo que D deve ser mantido estável após a descida do clock Valores típos (CMOS): tsu = 3ns e th = 2ns

  9. Master Slave Q Q m s Q Q D D Q D Clk Clk Clock Q Q Q (a) Circuito Clock D Q m Q = Q s (b) Diagrama de tempo Q D Q (c) Símbolo Gráfico Flip-Flop D Master-slave CLK = 1 master armazena e slave não muda CLK = 0 master não muda e slave armazena Sensível à borda de descida

  10. 1 P3 P1 2 5 Q Clock Q D 6 Q P2 3 Clock Q (b) Símbolo Gráfico 4 P4 D (a) Circuito Flip-Flop D sensível à borda de subida • Clk = 0  P1 = P2 = 1 • P3 = D • P4 = D • Clk =1  P3 e P4 são transmitidos através de 2 e 3 • P1 = D e P2 = D  Q = D e Q = D Obs - P4 e P3 DEVEM ESTAR ESTÁVEIS QUANDO CLK MUDA PARA 1

  11. Q D D Q a Clock Q Q Clk a Q D Q b Clock Q Q b Q Q D c Q a Q Q c Q b (a) Circuito Q c (b) Diagrama de Tempo Comparação de Flip-Flops D sensíveis a nivel e sensíveis a borda D

  12. Preset D Q Clock Q Clear (a) Circuito Preset Q D Q Clear (b) Símbolo Gráfico Flip-Flop Master-slave tipo D com Clear e Preset

  13. Preset Q Clock Q D Clear (a) Circuito Preset Q D Q Clear (b) Símbolo Gráfico Flip-Flop D sensível à borda de subida com Clear e Preset

  14. Flip-Flop D com reset síncrono

  15. Q D Q T Q Q Clock (a) Circuito ( ) Q t + 1 T Q T ( ) 0 Q t Clock ( ) 1 Q t Q T (b) Tabela Verdade (c) Símbolo Gráfico Q (d) Diagrama de tempo Flip-Flop tipo T (toogle)

  16. J Q D Q K Q Q Clock (a) Circuito Q ( t + 1 ) J K 0 0 Q ( t ) J Q 0 1 0 1 0 1 K Q 1 1 Q ( t ) (b) Tabela Verdade (c) Símbolo Gráfico Flip-Flop JK D = J Q + K Q J e K  entradas De controle FFs SR e T juntos

  17. Q Q Q Q 1 2 3 4 In Out Q Q Q Q D D D D Clock Q Q Q Q (a) Circuito Q Q Q Q = Out In 1 2 3 4 t 1 0 0 0 0 0 t 0 1 0 0 0 1 t 1 0 1 0 0 2 t 1 1 0 1 0 3 t 1 1 1 0 1 4 t 0 1 1 1 0 5 t 0 0 1 1 1 6 t 0 0 0 1 1 7 (b) Exemplo de uma seqüência Registrador de deslocamento com entrada e saída serial Registrador é um conjunto de n Flip-Flops FFs master-slave ou sensível à borda. Porque não sensível a nível ?

  18. Parallel output Q Q Q Q 3 2 1 0 Q Q Q Q D D D D Q Q Q Q Serial Clock Shift/Load input Parallel input Registrador de deslocamento com entrada paralela e serial e saída paralela

  19. 1 Q Q Q T T T Clock Q Q Q Q Q Q 0 1 2 (a) Circuito Clock Q 0 Q 1 Q 2 Count 0 1 2 3 4 5 6 7 0 (b) Diagrama de tempo Contadores Contador de 3 bits up-counter

  20. 1 Q Q Q T T T Q Q Q Q Q Q 0 1 2 (a) Circuit Clock Q 0 Q 1 Q 2 Count 0 7 6 5 4 3 2 1 0 (b) Timing diagram Contador de 3 bits down-counter Clock

  21. Derivação de contador síncrono up-counter Clock cycle Q Q Q 2 1 0 Q muda 1 0 0 0 0 Q muda 2 1 0 0 1 T0 = 1 T1 = Q0 T2 = Q0 Q1 T3 = Q0 Q1 Q2 Tn = Q0 Q1 ... Qn 2 0 1 0 3 0 1 1 4 0 0 1 5 1 0 1 6 1 0 1 7 1 1 1 8 0 0 0

  22. 1 Q Q Q Q T T T T Q Q Q Q 0 1 2 3 Clock Q Q Q Q (a) Circuito Clock Q 0 Q 1 Q 2 Q 3 Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 (b) Diagrama de tempo Contador síncrocno de quatro-bits up-counter

  23. Inclusão de sinais de enable e clear Enable Q Q Q Q T T T T Clock Q Q Q Q Clear

  24. Q Q D 0 Enable Q Q Q D 1 Q Q Q D 2 Q Q Q D 3 Q Output carry Clock Contador de 4 bits com FF D

  25. Enable 0 Q Q D 0 1 D 0 Q 0 Q Q D 1 D 1 1 Q Contador com entrada paralela 0 Q Q D 2 D 1 2 Q 0 Q Q D 3 D 1 3 Q Output carry Load Clock

  26. Enable 1 D Q 0 0 0 D Q 0 1 1 D Q 0 2 2 Load Clock Clock (a) Circuito Clock Q 0 Q 1 Q 2 Count 0 1 2 3 4 5 0 1 (b) Diagrama de tempo Contador modulo-6 com reset síncrono

  27. 1 Q Q Q T T T Q Q Q 0 1 2 Clock Q Q Q (a) Circuito Clock Q 0 Q 1 Q 2 Count 0 1 2 3 4 5 0 1 2 (b) Diagrama de tempo Contador modulo-6 com reset síncrono

  28. Enable 1 D Q 0 0 0 D Q 0 1 1 BCD D Q 0 0 2 2 Q D 0 3 3 Load Clock Clock Enable Clear D Q 0 0 0 D Q 0 1 1 BCD 1 D Q 0 2 2 D Q 0 3 3 Load Clock Contador BCD de 2 dígitos

  29. Contador em Anel 1000, 0100, 0010, 0001

  30. Contador Johnson Q Q Q 0 1 n – 1 Q Q Q D D D Q Q Q Reset Clock

  31. Inatalação de um FF D de um package LIBRARY ieee ; USE ieee.std_logic_1164.all ; LIBRARY altera ; USE altera.maxplus2.all ; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Resetn, Presetn : IN STD_LOGIC ; Q : OUT STD_LOGIC ) ; END flipflop ; ARCHITECTURE Structure OF flipflop IS BEGIN dff_instance: dff PORT MAP ( D, Clock, Resetn, Presetn, Q ) ; END Structure ;

  32. Memória LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY implied IS PORT ( A, B : IN STD_LOGIC ; AeqB : OUT STD_LOGIC ) ; END implied ; ARCHITECTURE Behavior OF implied IS BEGIN PROCESS ( A, B ) BEGIN IF A = B THEN AeqB <= '1' ; END IF ; END PROCESS ; END Behavior ;

  33. Codigo para um latch D gated LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY latch IS PORT ( D, Clk : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END latch ; ARCHITECTURE Behavior OF latch IS BEGIN PROCESS ( D, Clk ) BEGIN IF Clk = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ;

  34. Código para um FF D LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS ( Clock ) BEGIN IF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ;

  35. Código para um FF D usando WAIT UNTIL LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC ) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; Q <= D ; END PROCESS ; END Behavior ;

  36. FF D com reset assíncrono LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= '0' ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ;

  37. FF D com reset síncrono LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Resetn = '0' THEN Q <= '0' ; ELSE Q <= D ; END IF ; END PROCESS ; END Behavior ;

  38. Instanciação do módulo lpm_shiftreg LIBRARY ieee ; USE ieee.std_logic_1164.all ; LIBRARY lpm ; USE lpm.lpm_components.all ; ENTITY shift IS PORT ( Clock : IN STD_LOGIC ; Reset : IN STD_LOGIC ; Shiftin, Load : IN STD_LOGIC ; R : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END shift ; ARCHITECTURE Structure OF shift IS BEGIN instance: lpm_shiftreg GENERIC MAP (LPM_WIDTH => 4, LPM_DIRECTION => "RIGHT") PORT MAP (data => R, clock => Clock, aclr => Reset, load => Load, shiftin => Shiftin, q => Q ) ; END Structure ;

  39. Código um registrador de 8 bits com clear assíncrono LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY reg8 IS PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END reg8 ; ARCHITECTURE Behavior OF reg8 IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= "00000000" ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ;

  40. Código um registrador de n-bit com clear assíncrono LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 16 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= (OTHERS => '0') ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ;

  41. Código para um FF D com um multiplexador 2-para-1 na entrada D LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY muxdff IS PORT ( D0, D1, Sel, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC ) ; END muxdff ; ARCHITECTURE Behavior OF muxdff IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Sel = '0' THEN Q <= D0 ; ELSE Q <= D1 ; END IF ; END PROCESS ; END Behavior ;

  42. Código hierárquico para um shift-register de 4 bits LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY shift4 IS PORT ( R : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; L, w, Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END shift4 ; ARCHITECTURE Structure OF shift4 IS COMPONENT muxdff PORT ( D0, D1, Sel, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC ) ; END COMPONENT ; BEGIN Stage3: muxdff PORT MAP ( w, R(3), L, Clock, Q(3) ) ; Stage2: muxdff PORT MAP ( Q(3), R(2), L, Clock, Q(2) ) ; Stage1: muxdff PORT MAP ( Q(2), R(1), L, Clock, Q(1) ) ; Stage0: muxdff PORT MAP ( Q(1), R(0), L, Clock, Q(0) ) ; END Structure ;

  43. Alternativa para o shift register LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY shift4 IS PORT ( R : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; Clock : IN STD_LOGIC ; L, w : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END shift4 ; ARCHITECTURE Behavior OF shift4 IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF L = '1' THEN Q <= R ; ELSE Q(0) <= Q(1) ; Q(1) <= Q(2); Q(2) <= Q(3) ; Q(3) <= w ; END IF ; END PROCESS ; END Behavior ;

  44. Contador up-counter quatro-bits LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY upcount IS PORT ( Clock, Resetn, E : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ; END upcount ; ARCHITECTURE Behavior OF upcount IS SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN Count <= "0000" ; ELSIF (Clock'EVENT AND Clock = '1') THEN IF E = '1' THEN Count <= Count + 1 ; ELSE Count <= Count ; END IF ; END IF ; END PROCESS ; Q <= Count ; END Behavior ;

  45. Contador de 4 bits com carga paralela usando sinais INTEGER LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY upcount IS PORT ( R : IN INTEGER RANGE 0 TO 15 ; Clock, Resetn, L : IN STD_LOGIC ; Q : BUFFER INTEGER RANGE 0 TO 15 ) ; END upcount ; ARCHITECTURE Behavior OF upcount IS BEGIN PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN Q <= 0 ; ELSIF (Clock'EVENT AND Clock = '1') THEN IF L = '1' THEN Q <= R ; ELSE Q <= Q + 1 ; END IF; END IF; END PROCESS; END Behavior;

  46. Contador down-counter LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY downcnt IS GENERIC ( modulus : INTEGER := 8 ) ; PORT ( Clock, L, E : IN STD_LOGIC ; Q : OUT INTEGER RANGE 0 TO modulus-1 ) ; END downcnt ; ARCHITECTURE Behavior OF downcnt IS SIGNAL Count : INTEGER RANGE 0 TO modulus-1 ; BEGIN PROCESS BEGIN WAIT UNTIL (Clock'EVENT AND Clock = '1') ; IF E = '1' THEN IF L = '1' THEN Count <= modulus-1 ; ELSE Count <= Count-1 ; END IF ; END IF ; END PROCESS; Q <= Count ; END Behavior ;

  47. Data Extern Bus Clock R 1 R 2 Rk R 1 R 1 R 2 R 2 Rk Rk in out in out in out Control circuit Function Sistema digital com k registradores

  48. Conexão dos registradoes ao barramento

  49. Circuito de controle com um shift-register , , , R 2 R 3 R 1 R 2 R 3 R 1 out in out in out in w Q Q Q D D D Clock Q Q Q Reset

  50. , , , R 2 R 3 R 1 R 2 R 3 R 1 out in out in out in Reset w P Q Q Q D D D Q Q Q Clock Circuito de controle modificado

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