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Hello Bob is an example application developed by the FPX Applied Research Laboratory at Washington University, St. Louis. It includes features such as parsing UDP datagrams, sending datagrams back, string matching, and using SRAM interface.
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Hello Bob – An example application for the FPX Applied Research Laboratory Washington University, St. Louis http://www.arl.wustl.edu/arl/projects/fpx florian@arl.wustl.edu
Overview • Full FPX application (incl. RAD) • Parse UDP datagrams (using higher level framework) • Send datagram back (UDP Echo) • String match (“Hello”) • Use SRAM interface (to read name) • Replace data
Simplified example • Assume continuous data (easier for SRAM access) • Limit name length to 14 characters (incl. \0) • Name will fit in first cell • Don’t resize datagram (check for length)
Hello Bob Tarball • Download “hellobob.tar.gz” from http://www.arl.wustl.edu/arl/projects/fpx/workshop_0101/hellobob.tar.gz(save under D:\) • Unpack • “cd d:” • “tar xvzf hellobob.tar.gz” • Archive contains tree below FPX_TREE/RAD
Compiling fpxlib • Go to subdirectory “HelloBob/MODULES/LIB” • Compile processors by typing “make compile” in: • CellProcessor/sim • FrameProcessor/sim • IPProcessor/sim • UDPProcessor/sim
Dataflow HelloBob/MODULES/HelloBob/vhdl/hello_bob.vhdl
Memory access • Request memory when we receive frame • Sample grant (and store it) before we access memory • Save SRAM_GRANT on SOD • If we don’t get a grant use “John Doe” • Release memory after processing name
HelloBob module HelloBob/MODULES/HelloBob/vhdl/module.vhdl
RAD core HelloBob/TOP/RAD_HelloBob/vhdl/rad_hellobob.vhdl
Testbench HelloBob/TOP/RAD_HelloBob/sim/testbench.vhdl
Compile Testbench • Go to subdirectory “HelloBob/TOP/RAD_HelloBob/sim” • Compile RAD and testbench by typing “make compile”
Hello Bob • Send control cell to write “Bob” to SRAM • Is read from EGRESSIN.DAT • Send UDP datagram with “Hello…..” • Is read from INGRESSIN.DAT • Datagram with “Hello Bob” should return • IP addresses and UDP ports should be swapped
Start simulator • Go to subdirectory “HelloBob/TOP/RAD_HelloBob/sim” • Type “make sim” (simulator starts up) • Type “do testbench.do” (starts simulation)
Exercises • Implement Memory Statemachine • Generate SRAM_REQ • Sample SRAM_GRANT • Replace payload with name • Check terminating \0 • Watch for “o_” and shift HelloBob/MODULES/HelloBob/vhdl/hello_bob.vhdl
Testfiles • PROBE.DAT probe-request • SETVCI51.DAT control cell to change VCI from 0x32 to 0x33 • SRAM_BOB.DAT write name “Bob” to SRAM • UDP7HELLO.DAT datagram with “Hello” on port 7 • UDP7SALUT.DAT datagram with “Salut” on port 7 • UDP8HELLO.DAT datagram with “Hello” on port 8 • UDP51HELLO.DAT datagram with “Hello” on port 7, but VCI 0x33 (51) • UDP0HELLO.DAT TTL field is zero
Other tests • Send “Salut” instead of “Hello” (UDP7SALUT.DAT) • Type “cp UDP7SALUT.DAT INGRESSIN.DAT” • Run test again • Use port 8 instead of 7 (UDP8HELLO.DAT) • NOTE: testdata to HelloBob is read from INGRESSIN.DAT, testdata to the CCP is read from EGRESSIN.DAT
Hello <Your Name> • Login to jeeves (login on two terminals) • User: workshop## ex:workshop71(port 7 stack 1) • Password: workshop## • Invoking fpx_control • fpx_control fpx_number ex: fpx_control 7.1 • Writing String • enable rad logging: g rad • Write string: ws mod_num address ‘your name’ ex: ws 1 0 ‘Bob Smith’
Hello <Your Name> (cont) • Open log_file in second terminal • vi rad_log_xx.txt • Copy cell to clipboard • Highlight cell in vi • Right click on xterm in toolbar • Edit -> Copy X Selection -> To Clipboard • Paste Selection in notepad • Start -> Run -> notepad • Edit -> Paste • Save file as “EGRESSIN.DAT”
Different application VCI • We will change the application VCI (0x32 to 0x33) by sending a control cell to the CellProcessor • Create a new INGRESSIN.DAT from SETVCI51.DAT and UDP7HELLO.DAT • Type “cat SETVCI51.DAT UDP7HELLO.DAT > INGRESSIN.DAT” • Use UDP packet on channel 0x33 (51): UDP51HELLO.DAT
Probe Request • Sending a Probe-Request to the CellProcessor results in a “Generic CellProcessor Version 1.0” response • Use PROBE.DAT to send control cell
Change Probe Response • Change Probe Response in CellProcessor to “Hello Bob Version 1.0” HelloBob/MODULES/LIB/CellProcessor/vhdl/cellproc.vhdl
AAL5 Errors • Change payload word, do not change the CRC • CRC field is non-zero (=error) in FrameProcessor
TTL of zero • IP packets with TTL==zero are dropped (UDP0HELLO.DAT) • Frame does not appear on data output