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Chapter 5:

Chapter 5:. 4241 - Digital Logic Design. Synchronous Sequential Logic. Combinational Circuit. Inputs. Outputs. Memory Elements. Combinational Circuit. Inputs. Outputs. Flip-flops. Clock. Sequential Circuits. Asynchronous Synchronous. Latches. SR Latch. Q = Q 0. 0. 0. 1.

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Chapter 5:

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  1. Chapter 5: 4241 - Digital Logic Design Synchronous Sequential Logic

  2. Combinational Circuit Inputs Outputs MemoryElements Combinational Circuit Inputs Outputs Flip-flops Clock Sequential Circuits • Asynchronous • Synchronous

  3. Latches • SR Latch Q = Q0 0 0 1 0 Initial Value

  4. Latches • SR Latch Q = Q0 Q = Q0 0 1 0 0

  5. Latches • SR Latch Q = Q0 Q = 0 1 0 1 0

  6. Latches • SR Latch Q = Q0 Q = 0 1 1 Q = 0 0 0

  7. Latches • SR Latch Q = Q0 0 Q = 0 0 Q = 1 1 1

  8. Latches • SR Latch Q = Q0 0 Q = 0 1 Q = 1 Q = 1 0 1

  9. Latches • SR Latch Q = Q0 1 Q = 0 0 Q = 1 Q = Q’ 1 0 1

  10. Latches • SR Latch Q = Q0 1 Q = 0 1 0 Q = 1 Q = Q’ Q = Q’ 0 1

  11. Latches • SR Latch No change Reset Set Invalid Invalid Set Reset No change

  12. Latches • SR Latch No change Reset Set Invalid Invalid Set Reset No change

  13. Controlled Latches • SR Latch with Control Input No change No change Reset Set Invalid

  14. Controlled Latches • D Latch (D = Data) Timing Diagram C D Q t Output may change No change Reset Set

  15. Controlled Latches • D Latch (D = Data) Timing Diagram C D Q Output may change No change Reset Set

  16. C CLK Positive Edge CLK Negative Edge Flip-Flops • Controlled latches are level-triggered • Flip-Flops are edge-triggered

  17. D Latch (Master) D Latch (Slave) D D C Q D C Q Q CLK Flip-Flops • Master-Slave D Flip-Flop Master Slave CLK D Looks like it is negative edge-triggered QMaster QSlave

  18. D Q Q Q D Q Flip-Flops • Edge-Triggered D Flip-Flop Positive Edge Negative Edge

  19. Q J Q K Flip-Flops • JK Flip-Flop D=JQ’+K’Q

  20. D T Q Q Q Q Q T J Q T K Flip-Flops • T Flip-Flop D=JQ’+K’Q D=TQ’+T’Q=T Q

  21. D T Q Q Q Q Q J Q K Flip-Flop Characteristic Tables Reset Set No change Reset Set Toggle No change Toggle

  22. D T Q Q Q Q Q J Q K Flip-Flop Characteristic Equations Q(t+1) =D Q(t+1) =JQ’ + K’Q Q(t+1) =TQ

  23. Q J Q K Flip-Flop Characteristic Equations • Analysis / Derivation No change Reset Set Toggle

  24. Q J Q K Flip-Flop Characteristic Equations • Analysis / Derivation No change Reset Set Toggle

  25. Q J Q K Flip-Flop Characteristic Equations • Analysis / Derivation No change Reset Set Toggle

  26. Q J Q K Flip-Flop Characteristic Equations • Analysis / Derivation No change Reset Set Toggle

  27. Q J Q K Flip-Flop Characteristic Equations • Analysis / Derivation Q(t+1) =JQ’ + K’Q

  28. Q R D Q Reset Flip-Flops with Direct Inputs • Asynchronous Reset

  29. Q R D Q Reset Flip-Flops with Direct Inputs • Asynchronous Reset

  30. PR Q D Q Preset Reset CLR Flip-Flops with Direct Inputs • Asynchronous Preset and Clear

  31. PR Q D Q Preset Reset CLR Flip-Flops with Direct Inputs • Asynchronous Preset and Clear

  32. PR Q D Q Preset Reset CLR Flip-Flops with Direct Inputs • Asynchronous Preset and Clear

  33. Analysis of Clocked Sequential Circuits • The State • State = Values of all Flip-Flops Example AB= 0 0

  34. Analysis of Clocked Sequential Circuits • State Equations A(t+1)=DA =A(t) x(t)+B(t) x(t) =Ax + Bx B(t+1)=DB =A’(t) x(t) =A’x y(t)=[A(t)+ B(t)] x’(t) =(A + B) x’

  35. Analysis of Clocked Sequential Circuits • State Table (Transition Table) 0 00 0 10 0 01 1 10 0 01 1 00 0 01 1 00 A(t+1)=Ax + Bx B(t+1)=A’x y(t)=(A + B) x’ t t+1 t

  36. Analysis of Clocked Sequential Circuits • State Table (Transition Table) t t+1 t A(t+1)=Ax + Bx B(t+1)=A’x y(t)=(A + B) x’

  37. Analysis of Clocked Sequential Circuits • State Diagram AB input/output 0/0 1/0 0/1 0 0 1 0 0/1 1/0 0/1 1/0 0 1 1 1 1/0

  38. D Q x A Q y CLK Analysis of Clocked Sequential Circuits • D Flip-Flops Example: 0 1 1 0 1 0 0 1 A(t+1)=DA =Ax y 01,10 0 1 00,11 00,11 01,10

  39. Analysis of Clocked Sequential Circuits • JK Flip-Flops Example: 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 0 1 1 JA = B KA = B x’ JB = x’ KB = A  x A(t+1)=JA Q’A + K’A QA = A’B + AB’ + Ax B(t+1)=JB Q’B + K’B QB = B’x’ + ABx + A’Bx’

  40. Analysis of Clocked Sequential Circuits • JK Flip-Flops Example: 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 1 1 0 1 1

  41. Analysis of Clocked Sequential Circuits • T Flip-Flops Example: 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 TA = B x TB = x y = A B A(t+1)=TA Q’A + T’A QA = AB’ + Ax’ + A’Bx B(t+1)=TB Q’B + T’B QB = x  B

  42. Analysis of Clocked Sequential Circuits • T Flip-Flops Example: 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0/0 0/0 0 0 0 1 1/0 1/1 1/0 1 1 1 0 0/1 0/0 1/0

  43. Mealy and Moore Models Mealy Moore For the same state,the output does not change with the input For the same state,the outputchanges with the input

  44. Moore State Diagram State /Output 0 0 1 0 0 /0 0 1 / 0 1 1 1 1 / 1 1 0 / 0 1 0 0

  45. 1 0 0 0 0 /0 0 1 / 0 A x y 0 1 B 0 1 1 / 1 1 0 / 0 1 1 CLK Timing Diagram No effect x A 0 0 0 1 0 0 0 0 0 1 1 0 State B y

  46. A x y B CLK Timing Diagram 1/0 0/0 0/0 0 0 0 1 0/0 1/0 0/0 1 1 1 0 1/1 1/1 x A 1 0 State B y

  47. Design of Clocked Sequential Circuits • Example: Detect 3 or more consecutive 1’s 1 0 S0/0 S1/ 0 0 0 1 0 S3/ 1 S2/ 0 1 1

  48. 1 0 S0/0 S1/ 0 0 0 1 0 S3/ 1 S2/ 0 1 1 Design of Clocked Sequential Circuits • Example: Detect 3 or more consecutive 1’s 0 00 0 10 0 00 1 00 0 00 1 10 0 01 1 11

  49. Design of Clocked Sequential Circuits • Example: Detect 3 or more consecutive 1’s Synthesis usingDFlip-Flops 0 00 0 10 0 00 1 00 0 00 1 10 0 01 1 11 A(t+1)=DA (A,B, x) = ∑ (3, 5, 7) B(t+1)=DB (A,B, x) = ∑ (1, 5, 7) y(A,B, x) = ∑ (6, 7)

  50. Design of Clocked Sequential Circuits with D F.F. • Example: Detect 3 or more consecutive 1’s Synthesis usingDFlip-Flops DA (A,B, x) =∑ (3, 5, 7) = A x + B x DB (A,B, x) = ∑ (1, 5, 7) = A x + B’ x y(A,B, x) = ∑ (6, 7) = A B

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