1 / 8

Chapter 20 Smaller Tables

Chapter 20 Smaller Tables. Chien -Chung Shen CIS, UD cshen@cis.udel.edu. Problem. Big page table 32-bit address space (2 32 bytes) with 4KB (2 12 byte) pages and 4-byte page table entry 2 32 /2 12 pages and 4MB page table per process Problem: how to make page table smaller?

katell-lott
Download Presentation

Chapter 20 Smaller Tables

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Chapter 20Smaller Tables Chien-Chung Shen CIS, UD cshen@cis.udel.edu

  2. Problem • Big page table • 32-bit address space (232 bytes) with 4KB (212 byte) pages and 4-byte page table entry • 232/212 pages and 4MB page table per process • Problem: how to make page table smaller? • The simplest way • bigger pages • e.g., 16KB pages -> 1MB page table • internal fragmentation

  3. Hybrid Approach • Paging + segmentation PFN validprotpresentdirty 10 1 r-x 1 0 - 0 — - - - 0 — - - - 0 — - - 23 1 rw- 1 1 - 0 — - - - 0 — - - - 0 — - - - 0 — - - - 0 — - - - 0 — - - - 0 — - - - 0 — - - - 0 — - - 28 1 rw- 1 1 4 1 rw- 1 1 • Anythingbad? • toomanyinvalidPTEs

  4. Paging + Segmentation • One page table per segment • base (physical address of page table) + bounds • 3 page tables for code, heap, and stack • on TLB miss, use Segto decide which base/bounds SN = (VirtualAddress & SEG_MASK) >> SN_SHIFT // Seg VPN = (VirtualAddress & VPN_MASK) >> VPN_SHIFT AddressOfPTE= Base[SN] + (VPN * sizeof(PTE)) • Issues: • segmentation is not quite flexible (e.g., sparsely-used heap) • external fragmentation caused by page tables

  5. Multi-level Page Tables • How to get rid of those invalid regions in page table (instead of keeping them in memory) ? • turns linearpage table into something like a tree • chop up page table into page-sized units • if an entire page of PTEs is invalid, don’t allocate that page of page table at all • page directory PFN validprotpresentdirty 10 1 r-x 1 0 - 0 — - - - 0 — - - - 0 — - - 23 1 rw- 1 1 - 0 — - - - 0 — - - - 0 — - - - 0 — - - - 0 — - - - 0 — - - - 0 — - - - 0 — - - - 0 — - - 28 1 rw- 1 1 4 1 rw- 1 1

  6. Multi-level Page Tables Page directory entry (PDE)

  7. Multi-level Page Tables • Pros • page-table space allocated is proportional to amount of address space used • growing page table by getting more page frames (which could be anywhere in physical memory • Cons • on TLB miss, need two memory accesses to get translation info (one for page directory and one for PTE itself) • time-space trade-off • complexity: perfection is finally attained not when there is no longer anything to add, but when there is no longer anything to take away-- Antoine de Saint-Exupery

  8. Inverted Page Table • Instead of having many page tables (one per process), a single page table that has an entry for each physical page of the system • which process is using this page (frame) • which virtual page of that process maps to this physical page

More Related