CSCI206 - Computer Organization & Programming

1. CSCI206 - Computer Organization & Programming Constructing the Processor Revised by Alexander Fuchsberger and Xiannong Meng in spring 2019 based on the notes by other instructors. zyBook: 11.1, 11.2

2. Five classic components of computer organization

3. Basic MIPS Datapath/Control • To start off, we will design a datapath to support a basic subset of MIPS instructions: • Memory access: lw, sw • Integer arithmetic: add, sub, or, slt • Branch equal: beq

4. Fetch / execute cycle • Use the address in the PC register to fetch an instruction from memory (like a lw) • Read zero, one, or two registers (depending on instruction) • Perform specified operation • Write result to memory or zero/one register • Increment PC by 4 bytes • Repeat

5. Datapath v1.0 Interconnects What does this do? How/why does it work? Functional Blocks

6. MIPS Functional Blocks

7. Instruction Memory Instruction = Memory[ReadAddress]

8. Registers • Reads up to 2 registers • Writes to 1 register • controlled by RegWrite control signal ReadData1 = Reg[ReadRegister1]; ReadData2 = Reg[ReadRegister2]; if (RegWrite == 1) Reg[WriteRegister] = WriteData; When do we read/write? Registers are also known as register files.

9. ALU input1 • Two 32-bit inputs • One 32-bit ALU result • Zero is set when the ALU result is zero • useful for BEQ/BNE instruction • ALU operation control input determines ALU operation input2 ALUresult = input1 ALUop input2; Zero = ALUresult == 0;

10. Data Memory • Two 32-bit inputs • address • write data • One 32-bit output • read data • Two control signals • MemWrite (1 for sw) • MemRead (1 for lw) if (MemRead) ReadData = Mem[Address] if (MemWrite) Mem[Address] = WriteData

11. ** Control signals omitted The Basic MIPS Datapath

12. The Basic MIPS Datapath PC = 0x0040 0000 $t1 = 3, $t0 = 42 0040 0000: add $t2, $t1, $t0 0x0040 0000

13. The Basic MIPS Datapath 0x0040 0004 PC = 0x0040 0000 $t1 = 3, $t0 = 42 0040 0000: add $t2, $t1, $t0 0x0040 0000 0x0128 5020

14. The Basic MIPS Datapath 0x0040 0004 PC = 0x0040 0000 $t1 = 3, $t0 = 42 0040 0000: add $t2, $t1, $t0 0x0040 0000 0x9 0x0128 5020 0x8 0xA

15. The Basic MIPS Datapath 0x0040 0004 PC = 0x0040 0000 $t1 = 3, $t0 = 42 0040 0000: add $t2, $t1, $t0 0x0040 0000 3 0x9 0x0128 5020 0x8 42 0xA

16. The Basic MIPS Datapath 0x0040 0004 PC = 0x0040 0000 $t1 = 3, $t0 = 42 0040 0000: add $t2, $t1, $t0 45 0x0040 0000 3 0x9 0x0128 5020 0x8 42 0xA

17. Clocking the datapath • PC register is clocked so it doesn’t update until the instruction completes

18. The Basic MIPS Datapath 0x0040 0004 PC = 0x0040 0000 $t1 = 3, $t0 = 42 0040 0000: add $t2, $t1, $t0 45 0x0040 0000 3 0x9 0x0128 5020 0x8 42 0x10 Clock