Final Design Report Image Memory VLSI Senior Design Project

1. Final Design ReportImage Memory � VLSI Senior Design Project Brian Kociuba & Michael Rainville December 14, 2004 ECE 715

2. Table of Contents Introduction Goals Achieved Design Cell Design Cell Array Addressing The data bus System Design Testing DRC & LVS Simulations Timeline Conclusion

3. Introduction Image memory for fingerprint recognition and matching system Interfaces with fingerprint reader interface on input Interfaces with fingerprint matching algorithm interface on output

4. Introduction Memory stores 128 x 128 pixel grey-scale image 16,384 memory locations addressed by a 14 bit wide address code Each location stores 8 bits to represent a shade of grey Information for this report presented in a �bottom-up� method

5. Achieved Goals Maintains stable operation with write/read pulse widths of 10ns and under Write and read addressing is smooth Output and input match Data output is smooth and responsive to reads Data bus is shared and well isolated Physical layout fits on pad frame Low power consumption ~ 14.86nW over 200ns span

6. Design: Cell Design 6T SRAM design PMOS transistor size: 3 lambda(W) x 3 lambda(L) NMOS transistor size: 8 lambda(W) x 2 lambda(L) NMOS word line transistor size: 4 lambda(W) x 2 lambda(L) Cell size: 55 lambda(X) x 50 lambda(Y)

7. Design: Cell Design Chosen transistor size ratios allow for proper latching and switching times Cell does not force data line to 5V, just about 3.5V to allow for faster switching Data is internally inverted to create bit and notbit lines

8. Design: Cell Array One addressable location is eight cells wide Row and column decoder signals turn word line high by turning on an AND gate

9. Design: Array Design Custom AND gate activates a line of metal2 to turn word line high Transistor widths are similar to the ADK AND gate design but allow for easier routing This allows for an entire byte to addressed at once

10. Design: Array Design Memory array is a group of cascaded and flipped location arrays A small 4 x 4 array is used on the fabricated chip Each bit line is connected to a common bus of lines at the top of the array Addressing lines are routed through the array without breaks or vias

11. Design: Array Design

12. Design: Array Design

13. Design: Addressing Custom decoders used (AND type) 2 bit in ? 4 line out decoders Special delay incorporated into row decoder to fix an addressing line spike problem (0.5ns) AND gates used for enable decoding

14. Design: Addressing

15. Design: Addressing

16. Design: Addressing

17. Design: The Data Bus The data bus consists of: Write logic Precharge logic Sense amps Output buffers Each section explained piece by piece This portion of circuit is critical for data accuracy, verification and cleanliness Eight bits wide

18. Design: Write Logic The write logic is the input of the system Data is buffered One line is split into two, bit and inverted bit This is the only time we used ADK components in the physical layout

19. Design: Write Logic

20. Design: Precharge Logic This array of logic charges all lines to 5 volts when activated just before a read operation Each cluster of PMOS transistors switches on a logic zero Each precharge �cell� consists of two �charging� transistors of width 10 lambda and an �equalizer�

21. Design: Precharge Logic

22. Design: Sense Amp Logic Sense amps use a threshold switching voltage to boost or lower signal to its proper zero of five volt level The sense amp input is bit and inverted bit from the cell read from on its line The output is equal to bit One output leaves each sense amp

23. Design: Sense Amp Logic

24. Design: Output Buffer Logic The output buffers are used to clean signals on the output lines after the sense amps Each output buffer is a double inverter This custom setup has transistor geometries similar to that of an ADK buffer (one width is different) This is essentially a double inverter with the output inverter having �double-wide� transistors to drive the output

25. Design: Output Buffer Logic

26. Design: System Design The system was created piece by piece Each piece passed DRC, LVS, and timing tests separately After a sub-module passed its tests it was added to the system The system layout and routing was fully custom (besides the write logic) VDD and GND metal routed through system

27. Design: System Design

28. Design: System Design

29. Design: System Design

30. Testing The system and its pieces have been tested extensively in Eldo Custom pulses were created to test different scenarios that the system might face Power consumption was calculated in Eldo to be 14.86nW Eldo simulations and an LVS check are shown in the next slides

31. Testing The system layout passes LVS check with its logic It also passes DRC rules check

32. Testing

33. Testing Decoder testing was necessary to determine functionality of decoders

34. Testing The next step was to address cells with the decoders

35. Testing We tested one data line during initial data testing This line was �D0� A bit was written to an addressed cell

36. Testing The bit value was read from a cell on the �D0� data line to verify its cleanliness and accuracy to the input

37. Testing Another data line was tested the same way as �D0� Data was written to and read from the cell successfully Different Combinations of data were written to the cells

38. Timeline

39. Timeline By December 20th: Set small design on padframe Scale up design for large project Verify implementation Test large design in Mach TA