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Progress on the RCU Prototyping Bernardo Mota CERN PH/ED

Overview. Architecture. Trigger and Clock Distribution. Instruction Sequences. Current Capabilities. Present Status. Progress on the RCU Prototyping Bernardo Mota CERN PH/ED. On Behalf of: Carmen Gonzalez Gutierrez Roberto Campagnolo Roland Bramm Torsten Alt Kjetil Ullaland

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Progress on the RCU Prototyping Bernardo Mota CERN PH/ED

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  1. Overview Architecture Trigger and Clock Distribution Instruction Sequences Current Capabilities Present Status Progress on the RCU Prototyping Bernardo Mota CERN PH/ED On Behalf of: Carmen Gonzalez Gutierrez Roberto Campagnolo Roland Bramm Torsten Alt Kjetil Ullaland Jorgen Lien Are Martinsen Matthias Richter Heinz Tilsner Sebastian Bablok Christian Kofler ALICE TPC Meeting

  2. Overall Frontend System ALICE TPC Meeting

  3. FEC FEC FEC FEC Architecture FPGA Status Registers Slow Control Carmen Gonzalez Gutierrez talk DCS I2C bus Command Interpreter & Bus Switch RCU bus SIU Interface • ALTRO Interface • Instruction MEM • Pattern MEM • Active channel list • Result MEM Data Assembler 32 <- 40 ALTRO bus DDL ALICE TPC Meeting

  4. SWTRG RCU exec via DCS L1 L2 SWTRG WAIT programmable Data via DDL **** drift time L1 only L1 L2 RCU IF_L1 Test Beam Mode **** L1 External -L1 filter- L1-L2 RCU IF_L1 Final Operation Mode **** tw External -L1&L2 filter- L2 ALTRO Interface: Trigger Modes ALICE TPC Meeting

  5. 16’hxxxx IF_TRIGGER END RS_STATUS WAIT RS_L2CNT RS_L1CNT CHRDO 4’h1 4’h2 4’h6 4’hb 4’h9 4’ha 4’h3 16’hxxxx 16’hxxxx 16’hxxxx 16’hxxxx 16’hxxxx Nbr. Cycles CLK 19 19 19 19 19 19 19 0 0 0 0 0 0 0 channel add. PMREAD 4’h7 4’hx 19 16 15 12 11 0 Instruction Codebook Add. N loops JUMP/LOOP 4’h0 19 16 15 8 7 0 chann. add. bcast PMWRITE 4’h8 3’hx 19 16 15 13 12 11 0 16 15 ALICE TPC Meeting

  6. Testing Multi-Event Buffer & Readout with software trigger WRITE ‘N’ REG RPINC WPINC (L2) WAIT SWTRG (L1) *END* JUMP READ ‘N’ REG Accessing in infinite loop a given ALTRO Register CHRDO (Readout) Scope probing for electrical integrity check From ALTROs to DAQ w/ software trigger Examples of Instruction Sequences ALICE TPC Meeting

  7. Test Beam Mode Cardio Test - - - *END* JUMP RPINC READ HWADD ‘0’ IF_TRIGGER (L1) CHRDO (Readout) READ HWADD ‘1’ READ HWADD ‘i-1’ JUMP READ HWADD ‘i’ • From ALTROs to DAQ • w/ external L1-trigger: • ADC sampled data • Pattern stimuli Which cards are responding to basic register access? Examples of Instruction Sequences ALICE TPC Meeting

  8. *END* PMREAD PMWRITE Examples of Instruction Sequences Read Error register for mismatch error Pedestal Memory Test Checking ALTRO Pedestal memory access in a fast way ALICE TPC Meeting

  9. Raw Data Software Hardware Parameter Extraction ‘N’ configuration blocks RCU ALTRO/BC/RCU parameters Transporter to DAQ scripts buffer buffer Parameter Database Data Block Assembler FEC FEC FEC FEC Transporter to DCS scripts Current Configuration Paths ALICE TPC Meeting

  10. <1s 0.7s 3s Both paths FEC FEC FEC FEC Configuration and Readout Time • Overall configuration data: 7MByte/RCU - Worst case scenario: • 3200 active channels • 1000 samples/channel RCU Transporter to DAQ scripts buffer Transporter to DCS scripts buffer Readout: 3ms ALICE TPC Meeting

  11. Active Channel List 16bit = 1 ALTRO chip 1: Good 0: Non-working 256 words Channel not working will not be readout Active FEC List Updated by Slow control 32bit = max number of FEC / RCU Active Channel / FEC List Improving readout efficiency by storing the current status of one channel or board ALICE TPC Meeting

  12. m Proc & PCI-VME CORBO Module TTC VX TTC VI Current Trigger and Clock Distribution RCU board VME crate • Clock • L1-trigger • Trig.Messages Trigger Input TTC chip DCS board 10MHz FPGA 40MHz busy signal PC ethernet ALICE TPC Meeting

  13. Operation in High Trigger Rate 4.7KHz Event Rate 80MByte/s • Conditions: • 100 samples/channel • 128 channels • 40MHz Readout clk • 10MHz Sampling clk Exercise of full Readout Chain was performed successfully at KHz range trigger ALICE TPC Meeting

  14. √ ALTRO Configuration tested using both the DCS board and the DDL link √ Configuration of the RCU firmware from the DCS Board close to completion √ Slow Control through I2C fully operational measuring To, Currents and Voltages (Carmen Gonzalez Gutierrez talk) ? Improvement in readout time by a factor of 2: Replication of readout logic Present Status RCU Development √ • System fully tested and operational: • 2 branches (12 + 13 frontend cards) in a total of 3200 channels • DCS board running Linux on ARM processor and Ethernet link (Torsten Alt talk) • DAQ with both DATE system and lower level script language for config. • Communication between RCU and HLT fully operational • Installed in the T10 Area, ready for beam (Roberto Campagnolo talk) ALICE TPC Meeting

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