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The Effects of Operating Conditions on Speed and Power of Replica – Based SRAM Circuits

The Effects of Operating Conditions on Speed and Power of Replica – Based SRAM Circuits. Nika Sharifvaghefi Nicholas Kumar EE241 - Spring 2012. Sense-Amp in SRAMS. Instead of waiting for the actual bitline to discharge we take an early measurement Saves power Saves time. Sense-Amp Timing.

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The Effects of Operating Conditions on Speed and Power of Replica – Based SRAM Circuits

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  1. The Effects of Operating Conditions on Speed and Power of Replica – Based SRAM Circuits NikaSharifvaghefi Nicholas Kumar EE241 - Spring 2012

  2. Sense-Amp in SRAMS • Instead of waiting for the actual bitline to discharge we take an early measurement • Saves power • Saves time

  3. Sense-Amp Timing • When do we take the measurement? • Too early  error • Too late  waste of power and time • Conventional solution: Inverter chain

  4. Problems • Static fixed delay • Hard to find the proper amount without putting restrictions on usage condition • Have to pay a penalty (power) in normal conditions • PVT variations affect SRAM cells and inverters in different ways • Again have to put more slack

  5. Solution: Replica • Use SRAM cells instead of inverters • Affected the sameway by PVTvariations • Replica is not a fullcolumn

  6. Problems with Replica • Still have variations due to process • Have to add unnecessary slack • When Vdd goes down, we have fewer replica cells, so variation becomes important

  7. Different Solutions • Divide the bitline into independent parts • Works when #stages is low • Delay of extra logic between stages becomes important if #cells is low or #stages is high • Pick replica cells from a large set of configurable cells. Pick the best ones • Works very well • Requires post-silicon testing

  8. Different Solutions • Use a Timing Multiply Circuit • Use more replica cells than we should • We can’t use the raw replica output or else we’d get errors from sense-amp • Make up for the reduced delay by multiplying it using a TMC

  9. TMC • The clock signal goes through a forward path • As soon as the input signal goes up, the forward path gets transported to a backward path • If the backward path uses N times as many delay cells as the forward path does, the input delay gets multiplied by N+1

  10. Implementation • Implemented in Cadence using 90nm tech • Result:

  11. Conclusion • Using a TMC • Lowers the variation and therefore the unnecessary slack • Doesn’t need post-silicon test • Viable for low Vdd • Disadvantages • Adds to the area • Variation in delay cells

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