1 / 19

Interconnect by Optics Project Presentation

Interconnect by Optics Project Presentation. IMEC, Alcatel Bell, Avalon Photonics, Opto Speed, Helix, FCI, Nexans, RCI, PPC Electronics, LETI. Contents. Introduction Goals of the project Critical issues Partner List Study of optical interconnections in systems

kaz
Download Presentation

Interconnect by Optics Project Presentation

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Interconnect by OpticsProject Presentation IMEC, Alcatel Bell, Avalon Photonics, Opto Speed, Helix, FCI, Nexans, RCI, PPC Electronics, LETI

  2. Contents • Introduction • Goals of the project • Critical issues • Partner List • Study of optical interconnections in systems • The router demonstrator • The hardware for the proposed optical interconnection family • Electrical interface circuits • Plastic Optical Fibre • Glass sheet Pathway • Opto-electronic components: VCSELs and photodetectors • Hybridisation and packaging • Conclusion

  3. Introduction IO (interconnects by Optics) is a European project, co-funded by the EC, in the framework of the Information Society Technology (IST) programme Contract number is IST-2000-28358 In this project, parallel optical interconnections are developed. The project runs from September 1, 2001, to August 31, 2004

  4. Rationale for optical interconnections Current (and future) electronic systems need a vast amount of data transfer inside the system. • Metallic interconnections cannot deliver the required bandwidth, due to: • increased cross-talk • losses (and increased noise sensitivity) • physical limitation (dimensions of connectors etc…) Interconnection bottleneck • This happens at various levels in the electronic system: • chip access • on the board • at the connector level • at the backplane level Parallel optical interconnections are proposed as the solution to these problems

  5. Goals of the project To demonstrate a complete optical interconnect technology family in a major application area, being that of core IP routers. This family is based on 2-dimensional interconnects, with a direct integration of the optics on the digital CMOS IC. To identify (in an early stage of the project) the critical issues and the missing knowledge and/or technologies for this technology family and do research towards a solution of these issues/gaps. To ensure that the project generates direct opportunities for exploitation. 1 2 3

  6. Critical issues (1) • to develop optical interconnect design methodologies that can be integrated into E-cad environments • to develop a Plastic Optical Fibre with small core diameter, low loss, (<1dB/m) and high thermal stability (>100°C) • to develop cabling and connectorisation methods for 2D arrays of such POFs (single-ended 90° and dual ended 90° optical blocks) • to develop a POF-based technology for realising an optical layer as PCB-build up extension, allowing for complex interconnection patterns

  7. Critical issues (2) • to develop solutions for the use of glass sheet waveguides in PCB, as post solder build-up extension or pre-solder build-in PCB-layer. • to seek solutions for compactly integrated modules, consisting of a small-form-factor package for the CMOS IC, opto-electronics and an optical window, together witha passively aligned optical pathway interface. • to optimise driver and receiver circuitry for low power dissipation, small area and tolerance to non-uniformities in the electronic, opto-electronic and optical devices • to seek solutions that allow for testability and repairability

  8. Target parameters: • Key target parameters aimed for in this project are: • number of channels (at optical interfaces) ranging from 64 (first generation), to 256 (second generation) • IC-access channel density from 16/mm2 (first generation) to 64/mm2 (second generation) • data rate between 1.25 Gb/s (first generation) and 2.5 Gb/s per channel or higher (second generation) • This creates a solution with a huge aggregate • interconnect bandwidth, scalable to 5 and 10 Gbit/s per channel and higher, as the required performance goes up.

  9. Partner List • IMEC (prime)Belgium • Alcatel Bell N.V.Belgium • Avalon Photonics LtdSwitzerland • Opto Speed SASwitzerland • Helix AGSwitzerland • FCI 's HertogenboschThe Netherlands • NexansFrance • R.C.IFrance • PPC Electronic AGSwitzerland • CEA (LETI)France

  10. System study Top level analysis: Study of the nature of the expected bottlenecks in the next-generation high-performance electronic systems Set-up of a design methodology, and integrate in EDA tools Definition, development, prototyping and qualification of a high-performance electronic system: an optically interconnected IP router

  11. The router demonstrator Optical Digital CMOS IC with directly integrated opto-electronics and electronic interface circuits Electrical Power, Clock IP traffic in and out Data processing IP traffic in and out

  12. The hardware • The electrical interface circuits • driver circuits • receiver circuits • The opto-electronic components • emitters: VCSELs • detectors : InP photodiodes • The optical pathway • Plastic Optical Fibre (POF) • Glass sheets • The integration and hybridisation • A digital system: the IP router For use in the : 1. Technology demonstrators 2. IP router demonstrator

  13. Electrical interface circuits • CMOS driver and receiver requirements: • 250x250-125x125 µm2 cell size • 10 mW to 15 mW per channel power dissipation (complete link) • 1.25-2.5 Gbit/s per channel bit rate • 20 µApp receiver sensitivity • 5% drive current and sensitivity uniformity • Minimized electrical cross-talk (between analogue and digital circuit blocks)

  14. Plastic Optical Fibre Plastic optical fibre is the choice for the optical pathway, due to its flexibility, high numerical aperture, low cost and (potential) low loss. • POF-related work in the IO project : • Development of plastic optical fibres • Development of POF ribbons and POF connectors • Development of POF in flex

  15. Connectorisation & Optical interface Realisation of Plastic Optical Fibre: Novel concepts for multi-fibre connectors, using overmoulding of the POF’s Wiring of POF on flex foils:

  16. Glass sheet An alternative pathway is based on waveguides in glass sheets This pathway is directly integrated in the PCB

  17. The opto-electronic components Optical emitters: 2-D arrays of VCSELs The target performance parameters of the VCSEL arrays : · Threshold current: 1-2 mA . Emission wavelength 960 nm · Operating voltage: 1.6-1.7 V · Slope efficiency: 0.2-0.3 W/A · Beam divergence (FWHM): 16-20 ° · Bandwidth @ 5 mA: > 10 GHz (third generation) Optical emitters: 2-D arrays of detectors The target performance parameters for the PDs (at 25°C and 2.5V reverse bias are:) · Diameter of light sensitive area: 80 µm · Responsivity @ l = 960 nm: 0.5 A/W · Total capacitance: 600fF · Bandwidth: 5GHz · Optical cross-talk between neighbouring channels: 30dB

  18. Hybridisation and packaging • Packaging must take care of • optical coupling: the optical interface determines the alignment. • electrical connections: a flip-chip package. • protection of the CMOS and opto dies: a (quasi)-hermetic interface. A proposed approach: BGA (standard BGA,cavity down) Alignment fiducials CMOS Opto-chips Alignment plate Printed circuit board Optical connetor

  19. Conclusion • IO is a large project on optical interconnections : • development of high-performance components for 2-dimensional parallel optical interconnections, directly integrated on the CMOS • development of technology demonstrator and a system demonstrator For more information, news and latest status of the work, visit the IO web site at http://www.intec.rug.ac.be/IO

More Related