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Sticks Diagram & Layout

Sticks Diagram & Layout. Part II. Well and Substrate Taps. Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate (body) contacts / taps. Inverter Mask Set.

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Sticks Diagram & Layout

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  1. Sticks Diagram & Layout Part II

  2. Well and Substrate Taps • Substrate must be tied to GND and n-well to VDD • Metal to lightly-doped semiconductor forms poor connection called Shottky Diode • Use heavily doped well and substrate (body) contacts / taps

  3. Inverter Mask Set • Transistors and wires are defined by masks • Cross-section taken along dashed line

  4. V DD Inverter Out In GND

  5. CMOS Inverter Layout In GND V DD Out (a) Layout

  6. Transistor layout n-type (tubs may vary): L w

  7. Example: Inverter

  8. Example: NAND3 • Horizontal N-diffusion and p-diffusion strips • Vertical polysilicon gates • Metal1 VDD rail at top • Metal1 GND rail at bottom • 32 l by 40 l

  9. Example: O3AI • Sketch a stick diagram for O3AI and estimate area

  10. Wafer Wires and Vias • Creating wires (review): • Deposit insulator on chip (SiO2) • Deposit conducting material on chip • Selectively remove using photolithography • Use multiple layers so wires can cross over each other • Vias (Contacts) - Connect between layers • “cuts” etched through insulator • Metal connects between layers (with significant resistance)

  11. Wires and vias metal 3 metal 2 vias metal 1 poly poly p-tub n+ n+

  12. Example Problems - Parasitic Calculation (1/10) 30l metal1 1l=0.25µm poly ndiff Rmetal1=? Cmetal1=? Rpoly=? Cpoly=? Rndiff=? Cndiff=? Note: see Table 2-4, p. 80 for parameters

  13. Example Problems - Parasitic Calculation (6/10) 1l=0.25µm A What are the parasitic capacitances visible from point “A”?

  14. Stick diagrams (1/3) • A stick diagram is a cartoon of a layout. • Does show all components/vias (except possibly tub ties), relative placement. • Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

  15. Stick Diagrams (2/3) • Key idea: "Stick figure cartoon" of a layout • Useful for planning layout • relative placement of transistors • assignment of signals to layers • connections between cells • cell hierarchy

  16. Stick Diagrams (3/3)

  17. Example - Stick Diagrams (1/2) Alternatives - Pull-up Network Circuit Diagram. Pull-Down Network (The easy part!) Complete Stick Diagram

  18. Example - Stick Diagrams (2/2)

  19. Dynamic latch stick diagram VDD in out VSS phi phi’

  20. Stick Diagram XOR Gate Examples

  21. Hierarchical Stick Diagrams • Define cells by outlines & use in a hierarchy to build more complex cells

  22. Cell Connection Schemes • External connection - wire cells together • Abutment - design cells to connect when adjacent • Reflection, mirroring - use to make abutment possible

  23. Example: 2-input multiplexer • First cut:

  24. Sticks design of multiplexer • Start with NAND gate:

  25. NAND sticks VDD a out b VSS

  26. Refined one-bit Mux Design • Use NAND cell as black box • Arrange easy power connections • Vertical connections for allow multiple bits

  27. 3-bit mux sticks select’ select m2(one-bit-mux) select’ select VDD ai a2 oi o2 bi VSS b2 m2(one-bit-mux) select’ select VDD a1 ai oi o1 b1 bi VSS m2(one-bit-mux) select’ select VDD a0 ai oi o0 b0 bi VSS

  28. Multiple-Bit Mux

  29. Cell Mirroring, Overlap • Use mirroring, overlap to save area

  30. Example: Layout / Stick Diagram • Create a layout for a NAND gate given constraints: • Use minimum-size transistors • Assume power supply lines “pass through” cell from left to right at top and bottom of cell • Assume inputs are on left side of cell • Assume output is on right side of cell • Optimize cell to minimize width • Optimize cell to minimize overall area

  31. Layout Example Exterior of Cell Circuit Diagram.

  32. Example - Magic Layout • Overall Layout: 52 X 16

  33. Specification (what the chip does, inputs/outputs) Architecture major resources, connections Register-Transfer logic blocks, FSMs, connections Logic gates, flip-flops, latches, connections Circuit transistors, parasitics, connections You are Here Layout mask layers, polygons Review - VLSI Levels of Abstraction

  34. Levels of Abstraction - Perspective • Right now, we’re focusing on the “low level”: • Circuit level - transistors, wires, parasitics • Layout level - mask objects • We’ll work upward to higher levels: • Logic level - individual gates, latches, flip-flops • Register- transfer level - Verilog HDL • Behavior level - Specifications

  35. The Challenge of Design • Start: higher level (spec) • Finish: lower level (implementation) • Must meet design criteria and constraints • Design time - how long did it take to ship a product? • Performance - how fast is the clock? • Cost - NRE + unit cost • CAD tools - essential in modern design

  36. CAD Tool Survey: Layout Design • Layout Editors • Design Rule Checkers (DRC) • Circuit Extractors • Layout vs. Schematic (LVS) Comparators • Automatic Layout Tools • Layout Generators • ASIC: Place/Route for Standard Cells, Gate Arrays

  37. Layout Editors • Goal: produce mask patterns for fabrication • Grid type: • Absolute grid (MAX, LASI, LEdit, Mentor ICStation, other commercial tools) • Magic: lambda-based grid - easier to learn, but less powerful • Mask description: • Absolute mask (one layer for each mask) • Magic: symbolic masks (layers combine to generate actual mask patterns)

  38. Design Rule Checkers • Goal: identify design rule violations • Often a separate tool (built in to Magic) • General approach: “scanline” algorithm • Computationally intensive, especially for large chips

  39. Circuit Extractors • Goal: extract netlist of equivalent circuit • Identify active components • Identify parasitic components • Capacitors • Resistors

  40. Layout Versus Schematic (LVS) • Goal: Compare layout, schematic netlists • Compare transistors, connections (ignore parasitics) • Issue error if two netlists are not equivalent • Important for large designs

  41. Design Rules • Have to be respected when a given design is laid out. • Represent the physical limits of the manufacturing process. • Width, spacing, overlap, surround, extension. • www.mosis.org – detailed and up-to-date sets of design rules.

  42. Design Rules Checker, DRC • Is a program. • Checks that all polygons and layers from the layout database meet all of the manufacturing process rules, i.e. no violation of the design rules. • Checks for minimum spacing and minimum size, and ensures that combinations of layers form legal components.

  43. DRC Pass • Indicates that: • The design can be fabricated within the limitations of the manufacturing process. • The device fabricated can function.

  44. What happens if … • You ignore the DRC violations indicated to you? • You use bigger dimensions than the minimum stated by the Design Rules?

  45. Assignment • Read all the chapters we have covered. • Do all the related questions in the textbook. • What is GDSII and CIF?

  46. For Lab • Print out the DRC rules and take it along with you to lab. • Make sure you pass the DRC and LVS!!

  47. LVS, ERC, LPE, Tape-Out and Chapter 3 Tuesday, Jan. 20th

  48. Review • MOSIS • TSMC

  49. Layout Verification Tools • DRC • LVS • ERC • LPE

  50. DRC • What can you recall?

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