Presenter: Dilip Vasudevan Supervisor: Dr.Aristides Efthymiou University of Edinburgh

1. Partial Scan Test Generation for Asynchronous Circuits Based on Breaking Global Loops Presenter: Dilip Vasudevan Supervisor: Dr.Aristides Efthymiou University of Edinburgh 1 September 2008 20th UK Async Forum Manchester

2. Synopsis • Introduction • Test Methodology • Working Example • Results • Conclusion

3. Introduction Main challenges faced by applying ATPG technique to the asynchronous circuits are • Asynchronous circuits have loops which makes them cyclic circuit • Asynchronous circuits consist of memory element(C-element) other than latches. • The operation of C-element cannot be controlled during their normal operation compared to normal latch controlled by clock.

4. Contribution The contribution of the project AGLOB is A Graph is Strongly Connected if there is a path from each vertex in the graph to every other vertex. • Effective handling of cyclic asynchronous circuits to accommodate them for the usual synchronous test generation flow • Partial scanelement selection based on Breaking global loops • Global Loops broken by finding Strongly Connected Components • Automatic Test Pattern Generation for the partial scan design generated

5. AGLOB

6. AGLOB –APartial Scan Testgeneration for Asynchronous Circuits Based on Global LOop Breaking • Partial scan selection -Finding Strongly Connected Components • Global loops are broken by partial scan selection • Local loops are broken by applying cyclic to acyclic conversion • Fault simulation and test generation –Synopsys Tetramax

7. Cyclic Circuits with loops

8. Cyclic Circuits with loops

9. AGLOB Test Methodology Global Loops Broken DUT Netlist Scan Selection DFT Netlist Acyclic Converter Fault Simulation Processing Local Loops Acyclic Netlist Fault Coverage Tetramax Patterns

10. First Pass Second Pass L(1) 1 2 L(1) 1 2 L(2) 2 3 L(3) 3 4 6 Scan Elements = {1,3} L(4) 3 4 6 7 Scan Elements = {3}

11. Test generation C-element – (LOCAL LOOP)‏

12. Global loop in the ramreadsbuf Gates Constituting the loop in ramreadsbuf

14. Benchmark No of faults Fault coverage E [SS] Proposed C-element Half Hazard dff rcv-setup chu150 chu133 mp-forw-pack nak-pa ram-read-buf rpdft sbuf-ram-write sbuf-send-ctrl 26 22 48 40 25 56 54 60 82 90 62 110 94 - 40.0 87.9 21.4 100 97.1 96.9 100 100 100 100 100 59.3 - 100 97 85.7 100 97.1 96.9 100 100 100 100 100 94.9 88.23 100 76.19 76.67 77.78 89.19 91.23 92.77 76.78 96.34 76.78 96.25 90.36 Results – AGLOB TABLE I Fault Coverage Comparison of proposed method with Eichelberger's method and Spin SIM E – Eichelberger's SS - Spin-Sim

15. Benchmark Latch free FC (%) Full-scan FC (%) Proposed FC (%)‏ Loops chu133 45.56 85.71 91.23 1 local chu150 23.33 90.15 89.19 2 local mp-forward-packet 69.57 95.18 92.77 1g,1local ram-read-buf 40.71 93.29 96.34 1g,2local sbuf-ram-write 22.79 95.00 96.25 2 local Sbu-send-ctrl 16.20 94.16 90.36 3 local Results - AGLOB TABLE II Result – Fault Coverage Comparison of proposed methods with Latch Free, latch based designs

16. Results - AGLOB Fig 9. Scan latch Overhead Reduction in percentage

17. CONCLUSIONS • A Partial Scan based ATPG method for was introduced • Fault coverage - 76- 100% • Scan Area Overhead reduction - 0 – 66% (compared to full scan)‏ • Future work - Transistor Level Test Generation with new Fault Model

18. Thank You!