CPRE 583 Reconfigurable Computing Lecture 5: 9/7/2011 (VHDL to FPGA: A Tool Flow Overview )

CPRE 583Reconfigurable Computing Lecture 5: 9/7/2011(VHDL to FPGA: A Tool Flow Overview ) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://class.ece.iastate.edu/cpre583/

Announcements/Reminders • MP1: Delayed released by this evening (9/7) • HW1: Due Friday Midnight

Common Questions

Overview • Introduction to mapping VHDL to FPGA hardware • What you should learn • What are the major steps? • What is the basic purpose of each step?

Major Steps • Input Hardware Description Langue (HDL) • Synthesis • Map • Place & Route • Hardware configuration file generation

Graphical flow Implement Simulate Synthesize Map Place Route Download

Z <= (A and B) or C; Input VHDL description Major Steps (Text: Chapters 13-20) A Transform VHDL into primitive gates (synthesis) Z B C Z A LUT Transform primitive to technology dependent primitives (MAP) B C A LUT LUT LUT Associate primitive with specific Instances, and connect using Routing resources (PAR) B Z C LUT LUT LUT LUT LUT LUT A 000 000 000 Encode placement and routing description into a configuration file for programming a specific FPGA type B Z C 000 101 000 000 000 000

High Level Design Description • VHDL • Verilog • C type languages (e.g. handle C) • Typically auto transformed into VHDL or Verilog • Schematic capture (I believe ISE has this option) • Gate level (connecting structural components) • Statemachine bubble diagrams • High level graphical • Simulink/System Generator (Xilninx) • Simulink/DSP Builder (Altera) • http://www.youtube.com/watch?v=dSxqM7S2upA • System on chip embedded system design • Xilinx EDK: http://www.youtube.com/watch?v=STGiqlBRVms • Altera SoPC:

Synthesis • Application of Boolean logic theory • Technology independent representation • EDIF (Electronic Design Interchange Format) • Technology independent optimization • Combinational optimization • 2-level • Multi-level • Sequential optimization • FSM state reduction • retiming

EDIF representation • Gives a standard means to target a design to different vendors • Example EDIF file • http://en.wikipedia.org/wiki/EDIF

Combinational Optimization • This is a major area of active research! • ABC from Berkeley provides and open source tool • http://www.eecs.berkeley.edu/~alanmi/abc/ • This is a great starting place if you think you maybe interested in pursuing research in VLSI Computer Automation Design Tool development.

MAP (Technology Mapping: Chapter 13) • Translate device independent net list to device specific resources (for FPGAs a common device specific resource is a LUT) • Structural: • Maintains structure • Functional: • Will modify structure for optimization A Z A LUT Z B B C C

PAR (Place and Route: Chapters 14-17) • Place: Text Chapters 14 and 16 fundamentals • Route: Text Chapter 17 fundamentals • Tools and Challenge • VPR: http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html • Pathfinder • Open challenge (make some money?) • http://www.eecg.toronto.edu/~vaughn/challenge/challenge.html

Place (Chapter 17) • Bind each mapped resources to a physical device location • General Purpose • Placing resources without knowledge of high level structure. Guided by local connection between resources • Structured Guided • Makes assumptions about the structure of the circuit to guide placement. If circuit does not follow assumption will like give poor placement • User Guided Layout • User provides guidance to the algorithm to help with placement • Some way to provide this information • VHDL directives (e.g. relative location constraints RLOC) • GUI-based (e.g. Xilinx Floor Planner) • Can help to remove critical paths, and greatly decrease tool running time

Route (Text: Chapter 17) • Connect placed resources together • Two requirements • Design must be completely routed • Routed design meets timing requirements • Widely used algorithm “PathFinder” • PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs PathFinder (FPGA’95) • McMurchie and Ebeling • Reconfigurable Computing (Chapter 17) • Scott Hauch, Andre Dehon (2008)

Place & Route: How hard is it? • Let’s take a look at MP1’s layout

Configuration File Generation (Text: Chapter 19) • Convert place & routed design into a device configuration file (e.g. bitfile for Xilinx devices) • Download the configuration file to the FPGA

Next Class • VHDL Review: State Machines

Questions/Comments/Concerns • Write down • Main point of lecture • One thing that’s still not quite clear • If everything is clear, then give an example of how to apply something from lecture OR

CPRE 583 Reconfigurable Computing Lecture 5: 9/7/2011 (VHDL to FPGA: A Tool Flow Overview )