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Outline

Outline. Logical Operators vs. Bitwise Operators Continuous assignment Statement ( assign ) enable Level-Sensitive Circuits in Verilog Edge Sensitive Circuits in Verilog Test Bench with a vector file. Logical Operators. An Example of Logical Operators. Code. Execution. Bitwise Operators.

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Outline

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  1. Outline • Logical Operators vs. Bitwise Operators • Continuous assignment Statement (assign) • enable • Level-Sensitive Circuits in Verilog • Edge Sensitive Circuits in Verilog • Test Bench with a vector file

  2. Logical Operators

  3. An Example of Logical Operators Code Execution

  4. Bitwise Operators A bitwise operator interprets its operands as vectors and returns a vector.

  5. A Bitwise Operators Example

  6. assign • The assignment is said to be sensitive to the variables in the RHS expression because anytime a variable in the RHS changes during the simulation, the RHS expression is reevaluated and the result is used to update the LHS.

  7. An Example Using assign

  8. Execution of AOI_5

  9. Three-State Output • assign out=enable?in:1’bz; • If enable is true, then Y1 is evaluated. • If enable is false, then Y2 is evaluated.

  10. Example

  11. An AOI with a Tristate Driver

  12. Set-Reset (SR) latch

  13. A Transparent Latch

  14. A Verilog Model of a Transparent Latch

  15. Simulation Results for a Transparent Latch

  16. A Latch with Active-Low Reset and Active-High Enable

  17. A Latch with Active-Low Reset and Active-High Enable

  18. Testbench with a Test Vector File • Generate a clock • Load test vectors from a file • Edge Sensitive Operation • Load vectors on the rising edge of a clock • Check Resutls on the falling edge of a clock

  19. Clock Generation Statements after an always keyword is subject to an event control expression. The clock will be generated over and over again since it is not subject to any explicit event control expression in this example.

  20. Reading Binary Numbers from a File • $readmemb reads a file of binary numbers into an array called testvectors.

  21. Checking Load Test Vector Check the Results

  22. Input Vectors Purposely introduce an error in the test vectors to determine if the error message is working correctly.

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