Random Number Generator

1. Random Number Generator February 22, 2006 Top Level Integration Dmitriy Solmonov W1-1 David Levitt W1-2 Jesse Guss W1-3 Sirisha Pillalamarri W1-4 Matt Russo W1-5 Design Manager – Thiago Hersan Project Objective: Create a Cryptologically Secure Pseudo-Random Number Generator

2. Agenda • Status • Design Decisions • Timing Constraints • Timing Analysis • Power Analysis • Registers

3. Status Completed • C implementation • Architecture • Behavioral Design and Simulation • Gate-Level Design and Simulation • Preliminary Floorplan In Progress • Schematic Design and Simulation (90% Done) • Layout Unfinished • Extraction, LVS, post-layout simulation

4. Design Decisions • Adder, FSM and SRAM Design Finalized • Register Design Finalized • Counter Regs Based on JKFF • Data Regs Based on HLFF

5. Timing Constraints To understand our timing constraints, we have to go back and look our pipeline Stage 1 0) M1=M[i+32] A1=barrel(A) 1) X=M[i] A=A1+M1 2) M3=M[X] A=A1+M1 C1=(X==i-1) 3) Y1=A + (C1) ? Y : M3 4) Y1=A + (C1) ? Y : M3 Stage 2 0) Y=B+Y1 YL=B[13:0]+Y1[13:0] 1) Y=B+Y1 M4=M[Y[13:8]] C2=(I==Y[13:8]) 2) B=X+(C2) ? Y : M4 3) B=X+(C2) ? Y : M4 M[i]=Y 4) R[i]=B

6. What does this mean? • Since we have allotted the adder two ticks, the FSM one tick, and the SRAM half a tick… • The adder’s propagation delay SHOULD be double that of the FSM, which has a propagation delay that SHOULD be double that of the SRAM

7. Timing Analysis - Adder • Since our adder is so complicated we were unsure how to locate the critical path on the schematic by hand • We found the critical path of the adder to be from the B[4] pin to the S[31] pin using Pathmill

8. Timing Analysis - Adder Total Prop Delay: 1.44ns

9. Timing Analysis - FSM Total Prop Delay: 816ps

10. Timing Analysis - SRAM • The SRAM timing analysis had to happen in two parts. • A test row and a test column were constructed to isolate different components of the SRAM

11. Timing Analysis – SRAM Row Row Prop Delay: 445ps

12. Timing Analysis – SRAM Column Column Prop Delay: 290ps Total Prop Delay: 735ps

13. Putting it All Together

14. Registers • Using JKFF for Counter Regs

15. Registers • Using HLFF for Data Regs

16. Timing Analysis – Registers • JKFF • Rise time = 200p • Fall time = 200p • HLFF w/ Clear w/ 20fF load • Rise time = 140ps • Fall time = 70ps • HLFF w/ Load and Clear w/ 20fF load • Rise time = 200p • Fall time = 170p

17. Thanks! Any Questions?