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TPTTDO (Daisy Chain b/w FPGAs)

Probe for JTAG. TPTTDO (Daisy Chain b/w FPGAs). TPTTDO. TPTDI. TPTCLK. TPTTMS. Probe for SPI / I 2 C. TPSDA. TPSCL. TPSCLK. TPSEL0. TPSEL1. TPMOSI. TPMISO. NOTE : U35 is I2C Bus Isolator. Probe for IPM Bus. TPSCLB. TPSDAB. TPSDAA. TPSCLA. NOTE :

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TPTTDO (Daisy Chain b/w FPGAs)

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  1. Probe for JTAG TPTTDO (Daisy Chain b/w FPGAs) TPTTDO TPTDI TPTCLK TPTTMS

  2. Probe for SPI / I2C TPSDA TPSCL TPSCLK TPSEL0 TPSEL1 TPMOSI TPMISO NOTE : U35 is I2C Bus Isolator

  3. Probe for IPM Bus TPSCLB TPSDAB TPSDAA TPSCLA NOTE : U5 (bottom) is I2C Bus Isolator for IPMB A U6 (top) is I2C Bus Isolator for IMPB B

  4. Probe for GND TPG2 TPG1 TPG3 TPG4 TPG5 TPG6

  5. Probe driven by FPGA TP2_2 TP1_2 TP3_2 TP2_1 TP1_1 TP3_1 NOTE : TP1 , 2, and 3 are connected to AD3, AD4, and AD2, respectively.

  6. Power distribution (1) U17 In : VCC12 Out : VCC1V0 (20A) U16In : VCC12 Out : VCC3V3 (20A) Power ConverterIn : -48V Out: VCC12 PIM In : 48V Out : 3.3V & -48V

  7. Power distribution (2) U23 In : VCC12 Out : MGTAVTT (10A) U18 In : VCC12 Out : VCC1V8 (10A) U22In : VCC1V8 Out : VDDR1 (1.5V)(3A, linear) U29In : VCC3V3 Out : VCC2V5(3A, linear) U32In : VCC1V8 Out : VDDR2 (1.5V)(3A, linear) U21 In : VCC12 Out : MGTAVCC (10A)

  8. VCC12 @U16, U17 VCC12 VCC12 121 117 120 118 U16 U17

  9. VCC3V3 @U29 U29 VCC3V3 157

  10. MGTAVCC (1.0V) @U21 65 89 86 76 MGTAVCC U21

  11. MGTAVTT (1.2V) @U23 U23 MGTAVTT 122 90 132 105

  12. Management 3.3V @ PIM 19 3.3V (management) 20 3.3V (management)

  13. VCC1V8@FPGA VCC1V8 67_2 66_2 68_2 VCC1V8 66_1 68_1 67_1

  14. VDDR1@U22 VDDR2@U32 U22 Pin5 or Pin4. Pin5 looks easier to avoid short with PIn3 of GND U32

  15. Polarized Capacitors(330uF, Yellow big ones) VCC1V0 53_2 115 VCC3V3 155_2 VCC1V0 VCC2V5 75_2 156_1 55_2 VCC3V3 60_2 155_1 56_2 VCC3V3 156_2 56_1 54_2 59_1 VCC1V8 75_1 54_1 55_1 59_2 VCC3V3 53_1 60_2

  16. Polarized Capacitorsaround PIM C40 (470uF), C35, C36 (120uF) They have to have bar on downside as shown below

  17. Chip Orientation withTiny dot silkscreened on board (examples)

  18. CLOCK setting U27=GTXREFCLK 0 1 0 1 U11=SYSCLK Typical Setting 200 MHz {1, 0, 0, 1, 0, “X”} 156.25 MHz {1, 0, 1, 1, 0, “X”} 125 MHz {1, 0, 1, 1, 0, “X”}

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