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Minimization of *BMDs: Complexity and Algorithms

This paper discusses the complexity and algorithms for minimizing *BMDs (Binary Moment Diagrams) using don't care conditions. Two methods, min_polynomial and independent_dfs, are presented and experimentally proven to be effective in reducing the size of *BMDs. Future work includes modifying independent_dfs and applying don't care based minimization methods for the verification of divider circuits.

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Minimization of *BMDs: Complexity and Algorithms

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  1. Don´t Care Minimization of *BMDs:Complexity and Algorithms Christoph Scholl Marc Herbstritt Bernd Becker Institute of Computer Science Albert-Ludwigs-University 79110 Freiburg im Breisgau, Germany

  2. Introduction: Verification based on Decision Diagrams • Verification is an important task during the design of Integrated Circuits. • To verify combinational circuits: • Transform specification and implementation into canonicalrepresentations • Check for equivalence becomes check for equality. • Examples for canonical representations: • Binary Decision Diagrams (BDDs) • Binary Moment Diagrams (BMDs) • Multiplicative Binary Moment Diagrams (*BMDs) • ...

  3. Introduction: BDDs and *BMDs • BDDs: • directed acyclic graphs to represent Boolean functions • Succesful for verification of adders, control logic, ... • *BMDs • directed acyclic graphs to represent integer valued functions • Successful for verification of arithmetic circuits like multipliers

  4. Don´t caresare represented bycharacteristic functiondc: dc(y)=1  y cannot be applied here The Boolean functiondc(y) is represented by aBDD. The integer-valued functiong(y)for the circuit below the cut is represented by a*BMD. Don´t caresat thiscutare input combinations, which cannot be applied here. (Can bespecifiedorcomputedby image computations.) y y Interpret function values as integers, e.g. Motivation for DC-Minimization:Backward Construction When y is a don´t care, then we are allowed to change thefunction valueg(y)in order to minimize the *BMD for g to reduce memory consumption.

  5. Problem Formulation Given: *BMD B representing BDD DC representing Find: *BMD B*, such that and B* has minimal number of nodes among all *BMDs fulfilling the same property.

  6. v low(v) high(v) Decision Diagrams: BMDs, *BMDs (1) • Representation for integer-valued functions • Iterative positive Davio decomposition: • Representation as a directed, acyclic graph:

  7. v low(v) high(v) Decision Diagrams: BMDs, *BMDs (2) • Reduction rules: • eliminate identical subgraphs • eliminate v iff high(v) = 0 • *BMDs: More compact than BMDs due to additional reduction rules: • extract multiplicative constants of subfunctions into edge weights

  8. BMDs and Polynomials • Relationship between BMDs and polynomials over X • Example: • The size of BMD representing f is always less or equal to the size of the polynomial for f.

  9. +k -k +k Difficulties - Non-locality DC assignment for Decision Diagrams with Davio Decomposition: • Changing the function value for one input vector (don´t care) has not only local effect:

  10. Method min_polynomial (1) Idea: • Polynomial is lower bound on BMD (and *BMD) size. • Minimize size of polynomial for BMD/*BMD to get a small BMD/*BMD • Use don´cares to change coefficients, such that the number of 0-coefficients is maximized.

  11. don´t cares: (0,0),(1,1) -1 +1 +1 -1 -7 Method min_polynomial (2) • dc(0,0)=1 • dc(1,1)=1 Apply reduction rule!

  12. Method independent_dfs Idea: • Perform depth-first traversal of BMD • At each node v: • Use don´t cares to assign high(v) to 0 • Apply reduction rule to remove v.

  13. Experimental Results • Overview of several Benchmarks (40% don´t cares) • Node reductions by 75% (min_polynomial), 79% (independent_dfs)

  14. Conclusions / Future Work • We presented two methods do minimize *BMD / BMDs using Don´t Cares. • Experimental results proved them to be very effective in reducing the size of *BMDs. • Modification of independent_dfs to independent_bfs • Application of Don´t Care based minimization methods for verification of divider circuits.

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