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Integrated Circuit Devices

Integrated Circuit Devices. Professor Ali Javey Summer 2009. MOS Capacitors Reading: Chapter 16. MOS Capacitors. MOS: M etal- O xide- S emiconductor. MOS transistor. MOS capacitor. Ideal MOS Capacitor. Oxide has zero charge, and no current can pass through it.

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Integrated Circuit Devices

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  1. Integrated Circuit Devices Professor Ali Javey Summer 2009 MOS Capacitors Reading: Chapter 16

  2. MOS Capacitors MOS: Metal-Oxide-Semiconductor MOS transistor MOS capacitor EE143 – Ali Javey

  3. Ideal MOS Capacitor • Oxide has zero charge, and no current can pass through it. • No charge centers are present in the oxide or at the oxide-semiconductor interface. • Semiconductor is uniformly doped • M = S =  + (EC – EF)FB

  4. Ideal MOS CapacitorAt Equilibrium:

  5. Ideal MOS CapacitorUnder Bias • Let us ground the semiconductor and start applying different voltages, VG, to the gate • VG can be positive, negative or zero with respect to the semiconductor • EF,metal – EF,semiconductor = – qVG • Since oxide has no charge (it’s an insulator with no available carriers or dopants), d Eoxide / dx = / = 0; meaning that the E-field inside the oxide is constant.

  6. Inversion condition If we continue to increase the positive gate voltage, the bands at the semiconductor bends more strongly. At sufficiently high voltage, Ei can be below EF indicating large concentration of electrons in the conduction band. We say the material near the surface is “inverted”. The “inverted” layer is not gotten by chemical doping, but by applying E-field. Where did we get the electrons from? When Ei(surface) – Ei(bulk) = 2 [EF – Ei(bulk)], the condition is start of “inversion”, and the voltage VG applied to gate is called VT(threshold voltage). For VG > VT, the Si surface is inverted.

  7. Ideal MOS Capacitor – n-type Si

  8. Electrostatic potential, (x) Define a new term, (x) taken to be the potential inside the semiconductor at a given point x. [The symbol  instead of V used in MOS work to avoid confusion with externally applied voltage, V] Potential at any point x Surface potential | F | related to doping concentration F > 0 means p-type F < 0 means n-type

  9. Electrostatic potential S is positive if the bands bend\ …….? S = 2F at the depletion-inversion transition point (threshold voltage)

  10. p-Si VG < 0 Accumulation of holes Charge Density - Accumulation M O S p-type silicon accumulation condition The accumulation charges in the semiconductor are ……. , and appear close to the surface and fall-off rapidly as x increases. One can assume that the free carrier concentration at the oxide-semiconductor interface is a -function. x Charge on metal = QM Charge on semiconductor =  (charge on metal) |QAccumulation| = |QM|

  11. M O S p-Si VG > 0 QM w Depletion of holes Charge Density - Depletion p-type Si, depletion condition The depletion charges in Si are immobile ions - results in depletion layer similar to that in pn junction or Schottky diode. |q NA A W| = |QM| () (+) If surface potential is s, then the depletion layer width W will be

  12. M O S p-Si VG>>0 Charge Density - Inversion p-type Si, strong inversion Once inversion charges appear, they remain close to the surface since they are …….. Any additional voltage to the gate results in extra QM in gate and get compensated by extra inversion electrons in semiconductor. w QM Depletion of holes Inversion electrons: -function-like So, the depletion width does not change during inversion. Electrons appear as -function near the surface. Maximum depletion layer width W = WT

  13. MOS C-V characteristics • The measured MOS capacitance (called gate capacitance) varies with the applied gate voltage • A very powerful diagnostic tool for identifying threshold voltage, oxide thickness, substrate doping concentration, and flat band voltage. • It also tells you how close to an ideal MOSC your structure is. • Measurement of C-V characteristics • Apply any dc bias, and superimpose a small (15 mV) ac signal (typically 1 kHz – 1 MHz)

  14. Accumulation of holes x C-V: under accumulation M O S Consider p-type Si under accumulation. VG < 0. Looks similar to parallel plate capacitor. CG = Cox where Cox = (oxA) / xox p-Si VG < 0 CG is constant as a function of VG

  15. QM W Cox Cs Depletion of holes C-V: under depletion M O S Depletion condition: VG > 0 p-type Si VG > 0 CG is Cox in series with Cs where Cs can be defined as “semiconductor capacitance” Cox=ox A / xox Cs = Si A / W CG = Cox Cs / (Cox + CS) where s is surface potential CG decreases with increasing VG

  16. M O S p-Si VG >>0 QM W Depletion of holes Cox Cs Inversion electrons - function C-V: under inversion (high frequency) VG = VT and VG > VT Inversion condition s = 2 F At high frequency, inversion electrons are not able to respond to ac voltage. Cox=ox A / xox Cs = Si A / WT CG ( ) = Cox Cs / (Cox + CS) CG will be constant for VG  VT

  17. C-V: under inversion (low frequency) At low frequency, the inversion electrons will be able to respond to the ac voltage. So, the gate capacitance will be equal to the “oxide capacitance” (similar to a parallel plate capacitance). CG (  0) = Cox = ox A / xox low frequency Cox C high frequency Vg Vfb Vt accumulation depletion inversion Ideal MOSC (p-type Si) CG increases for VG  VT until it reaches Cox

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