Alien Hardware Diagnosis in ICs Using Path Delay Measurements

1. Alien Hardware Diagnosis in ICs Using Path Delay Measurements Spyros Tragoudas (PI) Dept. of Electrical and Computer Engineering Southern Illinois University, Carbondale, IL 62901

2. Project Overview and Description • Problem • Diagnosis of multiple delay-defective embedded segments • A scalable algorithmic approach to determine the location of defective segments • Project Description • Scalable Algorithmic Approach involving • Modeling integer expressions of potential defects • Bounded-Satisfiability modeling

3. Proposed Diagnosis Approach: an Overview • Excess delay along paths = Measured Post -silicon delays–Pre-silicon expected delays • Measured post-silicon delays are deterministic • Considering manufacturing process variationsresults in probability density functions (pdf) for pre-silicon expected delays • Discretize gate pdfs to create n circuit instances • Diagnostic solutions are obtained for each circuit instance • Finally, a recommendation is made by considering the union of all solutions

4. Modeling integer expressions of potential defects • Δ, granularity of measurement of the Automatic Test Equipment (ATE) • Excess delay along every path is represented as multiples of Δ • For example, • Consider a failing path • G4 + G6 + G12 • The path was tested for correct output at intervals of 1ps, i.e. Δ = 1ps • The correct output was observed after three intervals • Integer equivalent of the path • G4 + G6 + G12 = 3

5. Identifying potential defects For the paths in Figure 1, we have X1 + X9= 1 X2 + X9 = 0 X5 + X10 = 1 X5 + X11 = 1 X3 + X6 + X10 = 1 X3 + X6 + X11 = 1 X4 + X6 + X10 = 1 X4 + X6 + X11 = 1 X3 + X7 + X12 = 2 X4 + X7 + X12 = 2 X8 + X12 = 0 Possible assignments First Solution Set X1 = X3 = X4 = X5 = X7 = 1 and all other variables ‘0’ Second Solution Set X1 = X10 = X11 = 1, X7 = 2 and all other variables ‘0’ Third Solution Set X1 = X5 = X6 = 1, X7 = 2 and all other variables ‘0’ The third solution set exactly points to the defect locations • Fault free paths • X2 + X9 = 0 • X8 + X12 = 0 • Keep only equations corresponding to faulty paths • Remove fault free gate variables from all equations • Reduced set of equations X1 = 1 X5 + X10 = 1 X5 + X11 = 1 X3 + X6 + X10 = 1 X3 + X6 + X11 = 1 X4 + X6 + X10 = 1 X4 + X6 + X11 = 1 X3 + X7 = 2 X4 + X7 = 2 • An integer value can be assigned to each variable so that all equations are satisfied Figure 2: C17 with defects NSF IUCRC Embedded Systems

6. Recommending the most probable solution 1 When the SAT solver returns a large number of solutions Table 1: Prioritizing segments Heuristic H-sim(analysis of several segments simultaneously) • Recommend solution sets containing concurrently the top ranking segments • For segments {X1, X7, X5} we have, First Solution Set X1 = X3 = X4 = X5 = X7 = 1 Third Solution Set X1 = X5 = X6 = 1, X7 = 2 • First inspect the segments in the smallest collection

7. Recommending the most probable solution 2 When the SAT solver returns a large number of solutions Table 1: Prioritizing segments for physical inspection Heuristic H-inc(incremental physical analysis) • Applied during root-cause analysis (RCA) • In RCA the goal is to swiftly identify the actual defects from the suspect set • Choose the highest ranking segment • X1is a hit • Discard solution sets not containing X1 • Continue until only one solution set remains • Only X1, X7, X5 were physically inspected

9. Bounded-SAT Modeling • The formula Fin Conjunctive Normal Form (CNF) denotes a Boolean function [Silva’98] f : {0,1}n {0,1} • Fconsists of a product of clauses, where each clause C is a sum of literals l C = (l1 + l2+……..+ ln) • Each clause Ccorresponds to a measured path and each literal lcorresponds to a gate delay variable • Bounded-SAT requires that a predetermined number of literals from each clause be assigned ‘1’ • One of the satisfying assignments points exactly to the locations of alien components

10. Bounded-SAT Modeling • Each constraint of the ILP is modeled as a clause with non-negated literals. • Clauses are bounded based on the excess delay Consider the following set of reduced equations G1 + G9 = 1 G3 + G6 + G10 = 1 G8 + G12 =1 G3 + G7 + G12 = 2 The CNF is modeled as F = (G1 V G9) Λ (G3 V G6 V G10) Λ (G8 V G12) Λ (G3 V G7 V G12) 1 1 1 2 Bounds on Clauses

11. Variable replication in SAT modeling Initial Set of equations G1 + G9 = 1 G3 + G6 + G10 = 1 G8 + G12 =1 G3 + G7 + G12 = 2 After variable replication G1 + G9 = 1 G3 + G6 + G10 = 1 G8 + G12 =1 G3 + G71 + G72 + G121 + G122= 2 • Observe that G7 and G12 have two instances • G3 is in an equation which restricts its defect size to 1× Δ • A Boolean assignment can only assign a ‘0’ or ‘1’ to a particular variable • A Boolean ‘1’ assignment indicates a defect of size Δ • Variable replication is used to consider defects of varying sizes • For example,

12. Scalable Algorithmic Approach • Clauses per path Table 1: Overhead of both approaches NSF IUCRC Embedded Systems

13. ISCAS-85 • Rapid decrement in the number of alternative solution sets with increased number of measured paths

14. ISCAS-89 Benchmarks • Rapid decrement in the number of alternative solution sets with increased number of measured paths

15. ITC-99 Benchmarks • Rapid decrement in the number of alternative solution sets with increased number of measured paths

17. References [1] Ying-Yen Chen, Jing-JiaLiou, Diagnosis Framework for Locating Failed Segments of Path Delay Faults, in IEEE Transactions on VLSI Sytems, Vol. 16, No.6, June 2008. [2] Ying-Yen Chen, Min-Pin Kuo, Jing-JiaLiou, Diagnosis Framework for Locating Failed Segments of Path Delay Faults, in Proceedings of International Test Conference, 2005. [3] Tayade R., Nassif S., and Abraham J. Analytical model for the impact of multiple input switching noise on timing. In Proceedings of the 2008 Asia and South Pacific Design Automation Conference (Seoul, Korea, January 21 - 24, 2008). [4] Edward Flanigan, Spyros Tragoudas, Enhanced Identification of Strong Robustly Testable Paths, in Proceedings of International Symposium on Quality Electronic Design, 2007. [5] Ahish M Somashekar, Spyros Tragoudas, SAT based diagnosis of multiple delay defects in Integrated Circuits, submitted to International Test Conference 2012