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SEMICONDUCTOR MEMORIES. Chapter Overview. Semiconductor Memory Classification. Memory Architecture: Decoders. Array-Structured Memory Architecture. Hierarchical Memory Architecture. MOS NOR ROM Layout. MOS NOR ROM Layout. MOS NAND ROM. MOS NAND ROM Layout. Precharged MOS NOR ROM.
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6T-SRAM — Layout VDD M2 M4 Q Q M1 M3 GND M5 M6 WL BL BL
3T-DRAM — Layout BL2 BL1 GND RWL M3 M2 WWL M1
Row Decoders Collection of 2M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder
Semiconductor Memory Trends Memory Size as a function of time: x 4 every three years
Semiconductor Memory Trends Increasing die size factor 1.5 per generation Combined with reducing cell size factor 2.6 per generation
Semiconductor Memory Trends Technology feature size for different SRAM generations