Multi-core SoC Design is the Challenge! What is the Solution?

1. Multi-core SoC Design is the Challenge!What is the Solution? Drew WingardCTOSonics, Inc.

2. 2002 IVA Multi-core SoCs Look Alike! • Heterogeneous multi-core designs • Optimize for performance, cost, power • Incorporate legacy • Built from processor-based tiles • Encapsulate entire subsystem function, including control • Incorporate processing and storage to localize communication • Delivered together with associated firmware Sources: www.ti.com, www.arm.com,www.powervr.com 2004 DAC 2008: Multi-core Panel 8B

3. Multi-core SoC Performance is Determined by Interconnects and Memory Subsystems • Tiles need external memory bandwidth due to data set size • Tiles communicate with each other via external memory • SoC function is dominated by tile processing • SoC performance is dominated by DRAM communications • Must use DRAM bandwidth efficiently (too expensive to over design) • Must satisfy real time tile throughput & latency constraints • Managing communications performance is tougher each generation • Substantial new features, requiring much more bandwidth • Larger scale systems • More stringent power constraints DAC 2008: Multi-core Panel 8B

4. Multi-core SoC Design Solutions • Use a communications architecture that supports: • Mixing legacy and new tiles – decoupled network • Flexible interface semantics – socket protocols (such as OCP) • High throughput and concurrency – deep pipelines with threads • High efficiency and predictability – non-blocking flow control • Guaranteed bandwidth and latency – end-to-end QoS scheduling • Minimum energy and power – GALS and voltage domains • Earliest performance analysis – TLM-based data flow models • Predictable implementation path – physically optimized network • Example (available today!) • SonicsMX SMART Interconnect with MemMax memory scheduler DAC 2008: Multi-core Panel 8B