Process Bus Implementation on IEDs: Development Considerations

1. Process Bus Implementation on IEDs: Development Considerations

2. Overview • Conventional / Process Bus Substations • Topology example • Development of the IED • SV time alignment • Sampling frequency change • Frequency tracking • Estimation of lost SV

3. Conventional Substation

4. Process Bus Substation

5. Process Bus Substation

6. WAN Network Topology Example Telecontrol. Protection Management Maintenance Management LEVEL 2 (Substation) Subestation Bus IEC 61850-8-1 LEVEL 1 (Bay Position) IEC 61850-8-1 IEC 61850-9-2LE / IEC61869-9 LEVEL 0 (Switchgear) Merging Unit Merging Unit Merging Unit Process Bus

7. SV Alignment • Currents and Voltages can be measured by several MU • Each SV has a Sample Counter (smpCnt) used by the IED that receives the frames to make the alignment: • 50 Hz: 0 – 3999 • 60 Hz: 0 - 4799 • MU are synchronized (IRIG-B, PPS, IEEE1588). Reception on PPS signal forces the sample number 0, the rest are based on the internal MU clock • SV from different MU can arrive at different times. Delays due to: • MU processing time • Communication network MU works with 80samples/cycle delay must be considered

8. SV Alignment

9. Sampling Frequency Change • Two options to convert a conventional IED into process bus: • Adapt the filters to work with the new sampling frequency • Change the sample frequency and use the same filters • MU: 80 s/c • Frequency tracking • Protection algorithms • IED: 32 s/c

10. Frequency Tracking • Frequency tracking: algorithm that modifies the time between samples based on the frequency measurement to make the DFT window expand exactly one cycle • Sampling frequency of the MU is fixed (80 samples per 50 / 60 Hz cycle) without changing with the frequency • Frequency tracking: if SV are directly used, errors during off-nominal frequencies will appear. • The samples must span exactly one cycle. • Harmonic influence must be also taken into account

11. Estimation of Lost SV • SV can be lost • Lost SV can generate phasor errors during one cycle • Blocking will delay the operation for too long • Estimation on SV

12. Estimation of Lost SV • SV is consider as lost: • Delay time • Quality invalid • Synchronized flag FALSE • Estimation. Replaced by: • Zeros • Value of last SV • New SV after lost SV • Interpolation

13. Conclusions • A time delay must be considered when time alignment is performed • Decision between • Changing from the MU sampling rate to the conventional relay sampling (allows maintaining the digital filters and protection algorithms) • Work with the MU sampling rate • Frequency tracking is needed because of the fixed sampling rate of the MU. Harmonics influence must be taken into account. • Estimation of lost SV is a must. It should be developed to support SV lost also under harmonics presence.

14. Thank you Iñigo Ferrero inigo.ferrero@cggloblal.com