Advanced Implantation Detector Array (AIDA): Update & Issues

1. Advanced Implantation Detector Array (AIDA): Update & Issues presented by Tom Davinson on behalf of the DESPEC-DSSD/AIDA collaboration Tom Davinson School of Physics The University of Edinburgh

2. DESPEC: Implantation DSSD Concept • Super FRS Low Energy Branch (LEB) • Exotic nuclei – energies ~50-150MeV/u • Implanted into multi-plane, highly segmented DSSD array • Implant - decay correlations • Multi-GeV DSSD implantation events • Observe subsequent p, 2p, a, b, g, bp, bn … decays • Measure half lives, branching ratios, decay energies …

3. Implantation DSSD Configurations • Two configurations proposed: • 8cm x 24cm • “cocktail” mode • many isotopes measured simultaneously • b) 8cm x 8cm • high efficiency mode • concentrate on particular isotope(s)

4. DSSD Segmentation • We need to implant at high rates and to observe implant – decay correlations • for decays with long half lives. • DSSD segmentation ensures average time between implants for given x,y • quasi-pixel >> decay half life to be observed. • Implantation profile • sx ~ sy ~ 2cm • sz ~ 1mm • Implantation rate (8cm x 24cm) ~ 10kHz, ~kHz per isotope (say) • Longest half life to be observed ~ seconds • Implies quasi-pixel dimensions ~ 0.5mm x 0.5mm • Segmentation also has instrumentation performance benefits

5. DSSD • Technology well established • (e.g. GLAST LAT tracker) • 6” wafer technology • 10cm x 10cm area • 1mm wafer thickness • Integrated components • a.c. coupling • polysilicon bias resistors • … important for ASICs • Series strip bonding 8.95 cm square Hamamatsu-Photonics SSD before cutting from the 6-inch wafer. The thickness is 400 microns, and the strip pitch is 228 microns.

6. AIDA: DSSD Array Design Implantation depth? Stopping power? Ge b detector? Calibration? Radiation damage? Cooling? courtesy B.Rubio • 8cm x 8cm DSSDs • common wafer design for 8cm x 24cm and 8cm x 8cm configurations • 8cm x 24cm • 3 adjacent wafers – horizontal strips series bonded • 128 p+n junction strips, 128 n+n ohmic strips per wafer • strip pitch 625mm • wafer thickness 1mm • DE, Veto and 6 intermediate planes • 4096 channels (8cm x 24cm) • overall package sizes (silicon, PCB, connectors, enclosure … ) • ~ 10cm x 26cm x 4cm or ~ 10cm x 10cm x 4cm

7. AIDA: Instrumentation Requirements • Large number of channels required, limited available space and cost mandate • use of Application Specific Integrated Circuit (ASIC) technology. • Requirements • Selectable gain: low 20GeV FSR (use reset) • : • intermediate 1GeV FSR • : • high 20MeV FSR • Noise s ~ 5keV rms. • Selectable threshold: minimum ~ 25keV @ high gain ( assume 5s ) • Integral and differential non-linearity • Autonomous overload recovery ~ms • Signal processing time <10ms (decay-decay correlations) • Receive timestamp data • Timing trigger for coincidences with other detector systems • DSSD segmentation reduces input loading of preamplifier and enables • excellent noise performance.

8. AIDA: ASIC Concept • Example design concept • 1 channel of 16 channel ASIC (shown with external FPGA and ADC) • - FEE-integrated DAQ • - Digital data via fibre-optic cable to PC-based data concentrator/event builder courtesy I.Lazarus, CCLRC DL

9. AIDA: General Arrangement

10. DSSD/Kapton Package

11. ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC ADC ADC ADC ADC ADC ADC ADC ADC AIDA: 128 channel FEE Card Concept 16 ch ASIC (with ADC?) 128 detector signals in; 1 data fibre out Power Supplies and other components Virtex 4FX FPGA Fibre Driver (Laser) for Ethernet Ethernet MAC Estimated size: 80x220mm, Estimated power 25W per 128ch (800W total) courtesy I.Lazarus, CCLRC DL

12. NUSTAR: Common DAQ Interfaces Data output stage standard format and output medium e.g. 10G Ethernet fibre Correlate by timestamp Slow Control Common database loaded into local controllers over Ethernet Clock and Timestamp BUTIS Common Clocks 10/200MHz <100ps/km Front End Electronics Detector HV etc. Detector courtesy I.Lazarus, CCLRC DL

13. AIDA: System Concept BUTIS Timestamps PC Farm Data Output Switch Slow Control courtesy I.Lazarus, CCLRC DL

14. AIDA: Current Status • Edinburgh – Liverpool – CCLRC DL – CCLRC RAL collaboration • - 4 year grant period • - DSSD design, prototype and production • - ASIC design, prototype and production • - Integrated Front End FEE PCB development and production • - Systems integration • - Software development • Deliverable: fully operational DSSD array to DESPEC • Proposal approved EPSRC Physics Prioritisation panel meeting April 2006 • EPSRC award announcement letters received June 2006 • Detailed specification development has commenced • M0 – specification finalised and critical review

15. Resources • Cost • Total value of fEC proposal c. £2.3M (incl. PG c. £2.6M) • Support Manpower • CCLRC DL c. 4.2 SY FEE PCB Design • DAQ h/w & s/w • CCLRC RAL c. 3.5 SY ASIC Design & simulation • ASIC Production • Edinburgh/Liverpool c. 4.5 SY DSSD Design & production • FEE PCB production • Mechanical housing/support • Platform grant support CCLRC DL/Edinburgh/Liverpool

16. AIDA: Workplan

17. AIDA: Project Partners • The University of Edinburgh (lead RO) • Phil Woods et al. • The University of Liverpool • Rob Page et al. • CCLRC DL & RAL • John Simpson et al. • Project Manager: Tom Davinson • Further information: http://www.ph.ed.ac.uk/~td/AIDA

18. Outstanding Issues • Threshold • How low is low enough? • Package size • 10cm x 26cm x 4cm (10cm x 10cm x 4cm) • Range of implantation energies and species • 50-150MeV/u … ? • Corresponding ranges in Si • U 0.6 - 3.0mm • Sn 0.8 - 4.5mm • Ni 1.0 – 6.5mm • Energy and time resolution (decay) • < 10keV FWHM • < 10ns FWHM • Energy and time resolution (implant) • 1% … ? • ? • External trigger (to gamma/neutron/whatever arrays) • prompt? delayed? time resolution?

19. Acknowledgements Presentation includes material from other people. Thanks to: Ian Lazarus (CCLRC DL) Haik Simon (GSI) Berta Rubio (IFIC, CSIC University of Valencia)