Kuliah Rangkaian Digital Kuliah 6: Blok Pembangun Logika Kombinasional

1. Kuliah Rangkaian Digital Kuliah 6: Blok Pembangun Logika Kombinasional Teknik Komputer Universitas Gunadarma

2. Topic #6 – Combinational Logic Building Blocks • Tri-state buffers • XOR & XNOR • Decoders • Encoders • Multiplexers • Demultiplexers

3. EN A • Can tie multiple outputs together  one at a time is driven A·EN’+B·EN B Tri/Three-state buffers • Outputs: 0, 1, or Hi-Z (high impedance) CMOS transmission gate Hi-Z  Don’t care

4. 2-input XOR gates • True if and only if the two inputs are different • XNOR: complement of XOR • May be used as comparator

5. XOR and XNOR symbols • Why are they equivalent?

6. Gate-level XOR circuits • Can we make it using only NAND gates?

7. CMOS XOR with transmission gates IF B==1 THEN Z = !A; ELSE Z = A;

8. Parity computation – to detect single bit error Multi-input XOR? • What is X  Y  Z = ? • X’ · Y · Z + X · Y’ · Z + X · Y · Z’ + X’ · Y’ · Z’ • TRUE if odd number of inputs are TRUE • Associativity for XOR, just like AND & OR?

9. Parity tree • Faster with balanced tree structure

10. Decoders • Convert m-bit coded inputs into n-bit outputs • Typically m<n • E.g., n-to-2n, BCD decoders • Enable: prevent changes in output due to undesired changes in input

11. a f b g e c d BCD decoder EN D C B A a b c d e f g 0 x x x x 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 1 0 x x x x x x x 1 1 0 1 1 x x x x x x x 1 1 1 0 0 x x x x x x x 1 1 1 0 1 x x x x x x x 1 1 1 1 0 x x x x x x x 1 1 1 1 1 x x x x x x x • 4-bit input indicates the number to display, and thus control the on/off of the 7 segments. • Recall K-map minimization with Don’t cares …

12. Binary n-to-2n decoders • The kth output is 1 if the n-bit input has binary value of k • Ex: 2-to-4 decoder

13. 2-to-4-decoder logic diagram

14. F0 = x'y'z' F1 = x'y'z F2 = x'yz' F3 = x'yz F4 = xy'z' F5 = xy'z F6 = xyz' F7 = xyz x y z 3-to-8 binary decoders F0 F1 F2 F3 F4 F5 F6 F7 X 3-to-8 Decoder Y Z

15. Cin A B C S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 3-to-8 Decoder 0 1 2 3 4 5 6 7 1 0 0 0 1 S 1 0 1 1 0 1 1 0 1 0 Cin S2 S1 S0 1 1 1 1 1 A C B Realizing digital logic using decoders • Idea: • Canonical sum (of minterms) = decoder outputs connect to OR gate • Good and simple implementation when the circuit has many outputs each has few minterms • Example: Full adder • S(Cin, A, B) = S (1,2,4,7) • C(Cin, A, B) = S (3,5,6,7)

16. Decoder Encoder Encoders (vs. decoders) • m inputs, n outputs, m>n • Ex: 2n–to-n binary encoder

17. Inputs Outputs I I I I I I I I y2 y1 y2 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 I0 I1 I2 I3 I4 I5 I6 I7 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 Y2 = I4 + I5 + I6 + I7 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 y1 = I2 + I3 + I6 + I7 0 0 0 0 0 0 0 1 1 1 1 Y0 = I1 + I3 + I5 + I7 8-to-3 encoder example What if all Ik=0?

18. Multiplexers • Digital switches that select one of the n b-bit data as the output

19. 2-input multiplexer using CMOS transmission gates

20. Inputs Inputs I0 0 1 2 3 I0 4:1 MUX I1 I1 I2 mux Y Y Output I2 I3 I3 S1 S0 S1 S0 select select 4-to-1 multiplexer

21. I0 I0 I1 I1 Y Y I2 I2 I3 I3 0 1 2 3 2-to-4 Decoder S1 S0 S1 S0 4-to-1 Mux circuit diagram

22. I0 I1 I2 I3 4:1 MUX 2:1 MUX S1 S0 Y I4 I5 I6 I7 4:1 MUX S2 S1 S0 Larger multiplexers • Can be constructed using smaller ones … • Ex: 8=to-1 Mux

23. 16-to-1 multiplexer

24. MSI multiplexer example 74151A 8-to-1 multiplexer

25. b bits b bits n outputs Demux . . Data Input b bits Output Inputs s bits Mux Select Select Demultiplexers • Digital switches that connect the input to one of n outputs • Typically n = 2s

26. Y0 = D·S1'·S0' 2x4 Decoder Outputs S1 S0 Y1 = D·S1'·S0 Y0 = D·S1'·S0' Y2 = D·S1·S0' Y1 = D·S1'·S0 E Y3 = D·S1·S0 Data D Demux Y2 = D.S1·S0' D Y3 = D.S1·S0 S1 S0 select 1-to-4 demultiplexer • Implementing n-output b-bit Demux using b n-output Decoders • Connecting data bits to enables • Can we do it for Mux using Encoder?

27. Mux-Demux application example • Enables number of sources and destinations sharing a single communication channel

28. 0 1 0 1 0 1 1 0 0 1 2 3 4 5 6 7 F Mux Data Input Lines mux Mux Select Lines X Y Z Implementing n-variable func. using 2n-to-1 Mux • Methodology: • Express function in canonical sum form • Connect the n input variables to the Mux select lines, • For each Mux data input line Ii ( 0 £ i £ 2n – 1 ): • Connect 1 to Ii if i is a minterm of the function, • Otherwise, connect 0 to Ii. • Ex: F(X,Y,Z) = S(1,3,5,6)

29. 1 0 0 1 2 3 Value of X·Y Mux X Y Z F F Output Z Mux 0 0 0 1 1 0 0 0 1 1 0 1 0 0 1 Z 0 1 1 1 X Y 1 0 0 0 0 2 1 0 1 0 1 1 0 1 Z’ 3 1 1 1 0 Implementing n-variable func. using 2n-1-to-1 Mux • Idea: • Use only n-1 variables at the select lines • Connect the last one and its inverse to the input lines • Ex: F(X,Y,Z) = S(0,1,3,6) Mux Data Input Lines Mux Select Lines

30. Another example • F(x1,x2,x3,x4) = (0,1,2,3,4,9,13,14,15) using a 8-to-1 Mux (74151A) and an inverter.

31. Implementing n-variable func. using 2n-1-to-1 Mux • Express function F in canonical sum form • Choose n-1 variables connecting to mux select lines • Construct the truth table via grouping inputs based on select line values • Determine multiplexer input line i values by comparing the last input variable X and F: • Four possible mux input line i values: • 0 if F=0 regardless of the value of X • 1 if F=1 regardless of the value of X • F=X • F=X’