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TFT 공학 특론

TFT 공학 특론. 강의 2. Lattice. Energy band. Sodium : Na 원자 번호 11. Fermi energy level. Fermi energy level. - Conductor : Fermi energy level is located in the energy band. . Band gap energy, electron and hole. Insulator. Semiconductor. Band gap energy.

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TFT 공학 특론

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  1. TFT 공학 특론 강의 2

  2. Lattice

  3. Energy band Sodium : Na 원자 번호 11

  4. Fermi energy level Fermi energy level - Conductor : Fermi energy level is located in the energyband.

  5. Band gap energy, electron and hole Insulator Semiconductor Band gap energy - An excited Electron makes a hole in the valence band.

  6. Doping

  7. Crystal Si • sp3 Hybrid Molecular Orbital • Covalent Bonding • Diamond Structure • Eg = 1.1 eV

  8. Thin film a-Si:H 특성 * Dangling bond • μ= v/E ; v: 속도, E : 전기장 • μ= q/mν ; q: 전하량, m: 질량, ν:충돌 주파수

  9. Processing temperature/Substrate choice

  10. Gate Insulator : SiO2/SiNx Gate : 금속전극 E/S : SiNx Gate Insulator : SiO2/SiNx Gate : 금속전극 TFT Structure

  11. I-V characteristic - Linear region : • The I-V characteristic of TFTs can be described, in a first approximation, by • the same equations used for traditional NMOS transistors in crystalline Si. • μ isthe field effect mobility of the thin film semiconductor, a material property. • VTH is the TFT threshold voltage, which depends on both the semiconductor • and the gate insulator, and on their interface. - Saturation region :

  12. CLC • Since the LC dielectric constant depends on the orientation of the • molecules, the LC pixel capacitance varies significantly with applied voltage. • LC pixel capacitances in practical LCDs are typically 1pF or less.

  13. VHR • After the LC pixel capacitance is charged up to the data voltage, the TFT is • switched Off and the pixel electrode on the active array is floating. • The pixel capacitor should retain its data voltage for the remainder of the • frame time until the next address time. • The capacity to retain charge is often expressed in the voltage holding ratio • (VHR), which is defined as

  14. Storage capacitor/Ion • In addition to the LC pixel capacitance, most AMLCDs also have an • auxiliary storage capacitance connected in parallel to the LC capacitance. • The storage capacitor acts as a buffer to suppress the undesirable voltage • dependence and potential leakage current in the LC capacitance. • With a storage capacitor at each pixel it is easier to control the RMS • voltage on the pixel and therefore its gray level. • The ON current Ion of the switch should be sufficient to fully discharge the • LC pixel capacitance and charge it to the opposite polarity voltage Von • during the line time (Tline = Tframe/Nscan). This leads to

  15. Ioff The OFF current Ioff should be low enough to retain the charge on the pixel during the frame time where ΔV is the maximum tolerable voltage loss from the pixel capacitance during the frame time. For a 15 in. XGA display, Cst = 0.3 pF, CLC = 0.3 pF, and ΔV = 20 mV, we get In other words, the ON/OFF current ratio has to exceed six orders of magnitude.

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