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info@freehand-dsp

info@freehand-dsp.com. Agenda. About Freehand DSP OSCAR Technology MicroDSP Accelerators Development Tools. About Free h and DSP. Founded in November 1999; based in Stockholm, Sweden Owned by Affärsstrategerna AB and 4 co-founders Service-oriented IP Supplier

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info@freehand-dsp

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  1. info@freehand-dsp.com

  2. Agenda • About Freehand DSP • OSCAR Technology • MicroDSP • Accelerators • Development Tools

  3. About Freehand DSP • Founded in November 1999; based in Stockholm, Sweden • Owned by Affärsstrategerna AB and 4 co-founders Service-oriented IP Supplier • Licenses Application-Specific Programmable DSP cores • Supports optimizations and facilitate SOC integration • DSP H/W and S/W custom design services Passed Milestones • 03-01: Proof of concept - EchoDSP core • 09-01: Announced the Open SCalable ARchitecture

  4. Management team Harald Bergh, CEO, co-founder Former ASIC design manager at Ericsson Components, 20 years of experience from CMOS IC design as Full Custom designer, project manager and line manager. Dr. Dake Liu, VP System Engineering, co-founder Former Ericsson Senior. PhD in low power IC design, expert in processor and DSP design, many years of industry experience. Chairman Professor at Linköping Univ., Sweden. Stig Stuns, VP Software Engineering, co-founder Expert in algorithms and DSP software with many years of experience from several companies including Telia Research and Konftel. Nick Skelton, VP Hardware Engineering, co-founder Senior ASIC designer and project manager with 15 years of experience from companies including Marconi, Fujitsu and Ericsson. Gweltaz Toquet, VP Business Development Strong experience of the DSP industry through product marketing and business development positions with Texas instruments in Europe and USA.

  5. Business Model Off-the-shelf IP Building Blocks • Licensable IP cores: MicroDSP and Accelerators • Application Software Modules • Negotiable Upfront and Royalties fees Support and Services • S/W Development Tools (OSCAR Studio) • H/W and S/W Optimizations & Custom Design

  6. Agenda • About Freehand DSP • OSCAR Technology • MicroDSP • Accelerators • Development Tools

  7. DSP Technology Requirements • Flexibility (Programmability and Scalability) • Reduces time-to-market ! • Allows reuse across several products • Allows differentiation through new features Power-Efficiency • Extends battery life of portable applications • Increases port density in network infrastructure • Allows more features within fixed energy budgets • Makes new exciting applications work! • Cost-Efficiency • Allows cost reduction of existing applications • Allows more features within fixed cost budgets • Makes new exciting applications affordable!

  8. DSP Technology Trends (Chip Level) General Purpose DSP chips Application-Specific DSP chips (e.g. System-On-Chips)

  9. NEW! ASPDSP cores Tailored H/W and S/W partitioning + Optimised Cost-efficiency + Optimised Power-efficiency + Programmable DSP Technology Trends (Core Level) ASIC cores DSP algorithms implemented in H/W General Purpose DSP cores DSP algorithms implemented in S/W + Programmable - Poor Cost-efficiency - Poor Power-efficiency + Ultimate Cost-efficiency + Ultimate Power-efficiency - Not Programmable

  10. Open ASPDSP core Scalable Open SCalable ARchitecture Application-Specific Programmable DSP core = MicroDSP core + ApplicationSpecific Accelerators Acc. 1 MicroDSP core <45K gates 300MHz Acc. 2 To other MicroDSPs Acc. 3 Acc. 4

  11. MicroDSP = ultra small, low power programmable DSP core Low-end Communication Terminals, Hearing-aids, Headsets, Smart Toys, etc. ASPDSP core = MicroDSP + Application Specific Accelerators MicroDSP Mid-end Terminals, Digital Cameras, Audio Player, Residential Gateways, etc. DM Accelerators ASPDSP Cluster = Up to four ASPDSP cores MicroDSP 1 MicroDSP 2 Media Communication Terminals, Enterprise VoIP Gateways DM1 DM2 Scalable Performance DM3 DM4 MicroDSP 3 MicroDSP 4 ASPDSP System = Multiple ASPDSP clusters Carrier Class Media-over-IP Gateways OSCAR Application Coverage MicroDSP <45K Gates

  12. Flexibility= Programmability + H/W Scalability OSCAR-based ASPDSP cores YES Hardware Scalability Allows hardware upgrades and maximises the reuse ASPDSP cores Other ASPDSP cores ASIC cores (Dedicated H/W) ASIC cores (Dedicated H/W) General Purpose DSP cores General Purpose DSP cores NO NO NO YES YES Programmability Allows update of application standards and features through s/w

  13. OSCAR offers a unique combination of Efficiency and Flexibility OSCAR-based ASPDSP cores General Purpose DSP cores Other ASPDSP cores 25% 50% 75% 100% Flexibility to update and upgrade the targeted applications Dedicated H/W cores (ASIC cores) 25% 50% 75% 100% Functional Efficiency mW & silicon area for the targeted applications

  14. Agenda • About Freehand DSP • OSCAR Technology • MicroDSP • Accelerators • Development Tools

  15. MicroDSP Key Features • Fast*: Up to 300+MHz pre-layout * • Ultra-small*: 25K Gates @ 40MHz or 45K gates @ 300MHz • Low-power*: as low as 0.03 mW/MHz @ 1.0V • 16-bits fixed point (24-bit Instructions) • MAC unit (16X16 multiplier not pipelined) • 32-bit and 16-bit arithmetic unit • Logic, shift, and bit-field manipulation • 3 stages pipeline; only 1 cycle lost per jump • Tightly coupled interfaces to up to 4 accelerators • Multiprocessing interfaces to other MicroDSPs • S/W Development Tools: OSCAR Studio ( *: Estimates with 0.13um ArtisanTSMC library)

  16. MicroDSP DataPath Another 1 to 3 MicroDSP Accelerators (1-4) DMA BUS DM1 TM0 TM1 DM0 Register file and ports Processor bus collection MAC ALU MicroDSP DMx: Data Memories, TMx: Tap (coefficient) Memories

  17. Cycle formulas Cycle counts Program Memory (bytes) Real block FIR 13+N*(11+T) 1093 24*3= 72 Single sample FIR 13+T 29 13*3= 39 Complex block FIR 13+N*(36+4*T) 4013 49*3= 147 LMS adaptive FIR 17+4*T 81 24*3= 72 IIR 3+10*B 83 13*3= 39 Vector dot product 7+T 23 7*3= 21 Vector add 5+3*T 53 9*3= 27 Vector max. 3+T 19 4*3= 12 256-point FFT 17329 17329 96*3= 288 MicroDSP Benchmarks* *: Preliminary benchmarks

  18. Agenda • About Freehand DSP • OSCAR Technology • MicroDSP • Accelerators • Development Tools

  19. ECHO+ Accelerator • Patent Applied • Supports Adaptive Filtering • Performance: 4 Normalized-LMS taps per cycle • Typical Applications: • Carrier-class Voice Infrastructure • Hearing Instruments (?) • GatesCount: about 50K • Clock Speed: same as MicroDSP

  20. Echo Tail Length 0.13µm Artisan TSMC Lib. 32ms MicroDSP 64ms ECHO+ 128ms TOTAL # of channels (@ 300MHz) 252 ch. 252 ch. 136 ch. Total Number of Local Memories 4 4 8 Total Local Memory Size 84 kbit 32 kbit 116 kbit Total Local Memory Area 0.38 mm2 0.17 mm2 0.55 mm2 Logic Area 0.23 mm2 0.2 mm2 0.43 mm2 Total System Area 0.61 mm2 0.37 mm2 0.98 mm2 ECHO+ (continued) Number of G.168 channels per MicroDSP & ECHO+ system (Includes DTD, VAD, CNG; no auto-tail) Silicon Area Estimates MicroDSP & ECHO+ system optimized for 252 channels of G.168 at up to 64ms

  21. FFT+ Accelerator • Patent in Preparation • Supports FFT, IFFT • Performance: • Cycles/FFT: 2(N+8) + (N/2+8)*[log2(N)-2] • 1344 cycles for a 256 points Radix2 FFT • Typical Applications: • HiperLAN2 and IEEE 802.11B • Frequency domain voice enhancement • Gates count:about 30K • Clock Speed: same as MicroDSP

  22. Accelerators Roadmap Specification stage • CELP+ • Programmable Slave Accelerator • Supports any CELP standards (e.g. G.72x, GSM, AMR) • Up to 50 ch. of G723.1 on 150K gates (i.e. MicroDSP and 4 CELP+ at 300MHz) Concept stage • Frame parser • GPS • DCT, iDCT, ME, VLC for Video • 16-bit floating-point Audio • Etc.

  23. Agenda • About Freehand DSP • OSCAR Technology • MicroDSP • Accelerators • Development Tools

  24. OSCAR Development Flow RTL Description Define Efficiency Targets Pre-define H/W &S/W partition 1 Analyse Application Tasks Pick off-the-sleves Accelerators, or reuse your existing hardware IP to create new ones 2 Accelerator Models in C++ Select or Create Accelerator(s) Application Middleware IDE reconfiguration NO Run benchmarks on the Simulator and compare results with targets 3 Simulate Application Benchmarks Efficiency Targets Acceptable Efficiency? YES 4 Complete your SOC solution H/W and S/W Co-Design of the SOC

  25. OSCAR Studio Integrated Development Environment • Syntax highlighting editor • Assembler, Dis-Assembler, Linker • Cycle true Instruction Set Simulator / Debugger • Profiler • Library archiver • Accelerator development kit for MS Visual C++ • C Compiler / Source Level Debugger (2Q2002) Developed in Partnership with the Institute for System Programming of the Russian Academy of Sciences

  26. OSCAR Studio Features IDE features • Multiple document interface • Integrated profiler, debugger, disassembler and cycle-accurate simulator • CAS with pipeline visibility (Speed ~ 1.5 MIPS) • Full visibility of the accelerators datapath in the IDE Profiler • Supports both source and disassembly profile Accelerator Development Kit • Reduces time necessary to write Cycle Accurate Models

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