A SoC Simulator the newest component in Open64

1. A SoC Simulatorthe newest component in Open64 Wendong Wang, Tony Tuo, Kevin Lo Dongchen Ren, Gary Hau, Jun zhang, Dong Huang SimpLight Nanoelectronics Ltd http://svn.open64.net/svnroot/open64/sim/fsim/

2. Background

3. Challenges • Flexible • Easy to change ISA and modify micro-architecture • Speed • Fast enough for software development and compiler correctness verification • Co-verification • To speed up chip design cycle

4. Overview of SSIM

5. Challenges • Flexible • Speed • Co-verification

6. Flexibility • Decoupling implementation • function simulator implements the part which can be seen by programmer, and performance simulator implements the parts cannot be seen by programmer • Each component is defined as one class

7. Case Study • Sl1 and Sl2 retarget

8. Challenges • Flexible • Speed • Co-verification

9. Speed • Use template • most references are solved at compile time • Instruction caching • Page2 is non-decoded • When PC points to instr A, decoder invokes • Decoder will decode all instructions within the page • So all access of Page2 in the future will not invoke decoder

10. Speed Results for SSIM Table 1: Speed of SSIM with/without instruction caching (instructions per second)

11. Challenges • Flexible • Speed • Co-verification

12. Co-verification

13. Example: RTL module verification

14. Put all together Table 1: Instruction count for each component in Equalization

15. Other features -- debug • Use GDB+Eclipse for application debugging. • Embedded debug ability can accelerate system/driver software development.

16. Other features -- Profiling • Profiling module can turn on/off. • Can used lots of tools • PSIM • Instruction distribution tool • Branch analysis tool

17. Future Work • SoC architecture simulation • Current SSIM does not simulate bus traffic, hence it is not suitable to study SoC system performance issues • Accelerators • Power usage • Bus contention • MDL • Make SSIM can be retarget automatically

18. Thank You!