EEL 3705 / 3705L Digital Logic Design

1. EEL 3705 / 3705LDigital Logic Design Fall 2006Instructor: Dr. Michael FrankModule #9: Sequential Logic Timing & Pipelining

2. Monday, November 27, 2006 • Announcements: • SRS was due last Weds. • SLDS/TP is due this Weds. • Be sure to include a block diagram, & testing plan • Plan to test as many components as possible in simulation prior to prototype testing! • Interactive project demonstrations next week! • Sign up Wed. for a time-slot to demo your project • Today’s lecture: • Discuss present status of keyboard input example • Timing analysis of sequential circuits

3. Sequential Logic Timing Parameters • Any sequential storage element is subject to constraints on the relative timing of input, clock and output events. • Some important terms: • Setup timets – Min. req. time fr. start of valid input data to latching clock edge. • Hold time th – Min. req. time fr. latching edge to end of valid input data. • Ouput delay time tod – Worst-case time from latching clock edge to first appearance of corresp. valid output data. • A.k.a. “Clock-to-Q” time • These parameters, together w. combinational propagation delays, determine the max. tolerable operating frequency for a given sequential circuit. clk Q D Example: Rising edge-triggered D flip-flop tod ts th clk D valid invalid valid Q new value old value

4. clk ~clk D ~D ~s1 q ~r1 ~q Estimation of Timing Parameters • Given the internal structure of a storage element, and the delays associated with its internal components, we can estimate its overall setup, hold, and output delay times. • Example: Given that the prop. delay for NOT=1 ns, and NAND=2 ns, estimate ts, th, and tod for the master-slave D flip-flop shown below. SRheld SRtransp. clk SR transparent SR held ~clk Dtransp. D transparent D held D held Q D q ~s1 ~s2 d2 d1 undef. ~d1 undef. ~d2 ud. ~r2 ~r1 ~q ~d2 ~D 1 1 und. ~d1 undef. SR latch D latch 1 d2 d1 1 und. undef. Rising-edge-triggered D flip-flop madeof a clocked D latch driving a clocked SR latch,w. negative clock skew to reduce output delay und. d1 undef. ~d1 und. undef. ~s2 1 1 u u ~d1 ~r2 (Timing estimations on next slide) 1 1 u u d1 Q u d0 u d1 d2

5. clk ~clk D ~D ~s1 q ~r1 ~q Setup/Hold Time Estimationsfor this Example • Setup time ts = 4 ns, because • Path to set D latch B+D+F+E (7 ns) must beat lockdown signal A+C&A+D (3 ns). • Hold time ts = 3 ns, because • A+C (3 ns) must finish before it’s safe to allow D to fluctuate • Output delay tod = 7 ns, because • Critical path is B+D+F+H+J+I (11 ns), minus setup time of 4 ns before clock edge SRheld SRtransp. SR transparent SR held Dtransp. D transparent D held D held clk d2 d1 undef. ~clk A ~d1 undef. ~d2 ud. q D Q ~d2 1 1 ~s2 und. ~d1 undef. ~s1 C G E I 1 d2 d1 1 und. undef. und. ~q d1 undef. F J H D ~r2 ~r1 B ~d1 und. undef. ~D ~s2 SR latch 1 D latch 1 u u ~d1 ~r2 1 1 u u d1 Q u d0 u d1 d2

6. Sequential Logic Timing Analysis • What is the minimum clock period tper,min and max freq. fmax for this sequential circuit? • One constraint: • New state D′ must be ready by at least a setup-time prior to next edge. • tper > tod + tpd + ts • Thus tper,min = tod + tpd + ts, • and so fmax = 1/(tod + tpd + ts). D Q ts, th, tod Combinationalstate-update logicw. prop. delay tpd D′ tod ts th ts th clk D valid invalid valid Q tpd

7. Why is Hold Time important? • Consider the behavior of a sequential circuit immediately after a clock edge… • If the minimum (fastest-case) output delay plus propagation delay is less than the storage element’s hold time, • The flip-flop’s input can get corrupted before we are finished locking its state! • The new-state signal “races” all the way around the circuit and interferes with itself. • This is an example of a “race condition” hazard. • These can be avoided entirely by using “two-phase non-overlapping clocks” (next slide) D Q ts, th, tod Combinationalstate-update logicw. prop. delay tpd D′ A race condition exists if tod + tpd < th.

8. Two-Phase Non-overlapping Clocks • Suppose that the two latches making up a flip-flop are driven by independent clocks… • That is, the 2nd is not simply the complement of the first… • If the duty cycles (active periods) of the clocks are non-overlapping, • then both latches are never transparent at the same time • For there to be a race condition is then impossible! Φ1 Φ2 latch1 latch2 next-statelogic latch 1transparent Φ1 Φ2 latch 2transparent period of non-overlap

9. Generating two-phase nonoverlapping clocks from single-phase clocks • What if two-phase non-overlapping clocks aren’t provided to you? • Never fear, you can make them with a NOR-based structure, like an unclocked SR latch… • The falling edge on one of the clock outputs causes a subsequent rising edge on the other… clk clk Φ1 clk′ Φ1 Φ2 clk′ Φ2

10. Clock Frequency Dividers • What if the available clock signals are too fast for your design, and you need a slower clock? • This is easy, just use an n-bit counter to divide the input clock frequency by 2n… • You can also use a modulo-m counter with its overflow bit clocking a T flip-flop to obtain a frequency reduction by any even factor 2m. clk q0 frequency f/2 n-bitcounter q1 (freq. f) frequency f/4 q2 frequency f/8 … qn-1 frequency f/2n

11. Another way to generate 2-phase non-overlapping clocks • Assuming that you already have a working edge-triggered sequential counter… • This method generates non-overlapping output clocks with frequencies ¼ that of the input clock. • Note there is also a significant period of non-overlap. e0 Φ1 clk e1 2-bitcounter t1..0 decoder e2 Φ2 e3

12. JK Flip-Flops Move slide toearlier module • A JK latch or flip-flop is like an SR flip-flop (with J=set, K=reset), but… • When both J and K inputs are on, toggles (complements) the flip-flop’s state • This input combination was disallowed for the SR case • An (unclocked or level-sensitive) JK latch is not very useful because its output (when J=K=1) is unstable, and hence unpredictable. ck Q J D K Edge-triggered JK flip-flopfrom an edge-triggered D flip-flop

13. T (Toggle) Flip-Flop • Basically, a JK flip-flop where J=K=T. • When T is on, output is toggled • when T is off, output remains unchanged • Like with JK, output is unstable unless transitions are edge-triggered ck J T Q K (when T=1)

14. Pipelined Sequential Logic • What if your next-state logic becomes very deep and complicated? • Its propagation delay will likely be high… • And this means your clock frequency will be low. • This hurts the performance (throughput) of your design. • A widely-used approach to fix this problem: • Divide your deep logic into some number d of sequential stages (where d is called the “pipeline depth”)… • with relatively shallow, fast logic between them • You can then clock new inputs into the circuit at (nearly) d times higher frequency! • Side effect: Your design now maintains d states in parallel! • Your application must be parallelizable for this to be helpful. • Note: Pipelining can improve throughput, but not the latency (time from input to output) to process individual data.

15. Non-pipelined vs. pipelined sequential designs For pipeline depth d=2: • Non-pipelined computes: • xt+1 = zt= g(f(xt)) • Pipelined computes: • yt+1 = f(xt); xt+2 = zt+1 = g(yt+1) = g(f(xt)) • state on even cycles • And simultaneously: • yt+2 = f(xt+1); xt+3 = zt+2 = g(yt+2) = g(f(xt+1)) • state on odd cycles clk Slowclock z x g(f(x)) same function! clk Fasterclock z f(x) g(y) x y Are both of these statesrepresenting something useful?Depends on your application!