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COE 1502 Design Synthesis

COE 1502 Design Synthesis. Synthesis Theory. Idea: “Compile” VHDL into a cell-level netlist A netlist is a graph Vertices represent cells (such as gates, latches, etc.) Edges represent interconnection wires To do this, we need VHDL A technology cell library

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COE 1502 Design Synthesis

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  1. COE 1502Design Synthesis

  2. Synthesis Theory • Idea: • “Compile” VHDL into a cell-level netlist • A netlist is a graph • Vertices represent cells (such as gates, latches, etc.) • Edges represent interconnection wires • To do this, we need • VHDL • A technology cell library • Place-and-route netlist onto FPGA/ASIC • To do this, we need • Netlist • CLB specification and routing matrix (FPGA) • Output is FPGA routing bitmap

  3. A port port port OR2 AND2 port B D E C Netlists • Leonardo Spectrum’s output format is a text EDIF netlist • Example: instance OR2 as ix1 instance AND2 as ix3 ix1 A B D ix3 D C E Note that AND2 and OR2 are technology cells

  4. Netlists • Actual Leonardo output: (library alu (edifLevel 0) (technology (numberDefinition )) (cell example (cellType GENERIC) (view struct (viewType NETLIST) (interface (port A (direction INPUT)) (port B (direction INPUT)) (port C (direction INPUT)) (port E (direction OUTPUT))) (contents (instance ix1 (viewRef INTERFACE (cellRef OR2 (libraryRef PRIMITIVES )))) (instance ix3 (viewRef INTERFACE (cellRef AND2 (libraryRef PRIMITIVES )))) (net A (joined (portRef A ) (portRef p0 (instanceRef ix1 )))) (net B (joined (portRef B ) (portRef p1 (instanceRef ix1 )))) (net C (joined (portRef C ) (portRef p3 (instanceRef ix3 )))) (net E (joined (portRef E ) (portRef out (instanceRef ix3 )))) (net D (joined (portRef out (instanceRef ix1 )) (portRef p2 (instanceRef ix3 )))))))) (design example (cellRef example (libraryRef alu )))) (edif example (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timestamp 2003 01 23 17 13 48) (program "LeonardoSpectrum Level 3" (version "2002b.21")) (author "Exemplar Logic Inc"))) (external PRIMITIVES (edifLevel 0) (technology (numberDefinition )) (cell OR2 (cellType GENERIC) (view INTERFACE (viewType NETLIST) (interface (port (rename p0 "in[0]") (direction INPUT)) (port (rename p1 "in[1]") (direction INPUT)) (port out (direction OUTPUT))))) (cell AND2 (cellType GENERIC) (view INTERFACE (viewType NETLIST) (interface (port (rename p2 "in[0]") (direction INPUT)) (port (rename p3 "in[1]") (direction INPUT)) (port out (direction OUTPUT))))))

  5. ALU Wrapper • Your ALU design must be placed into a wrapper before you perform synthesis • The ALU wrapper is located in the COELib library • Wrapper shares a signal namespace with its wrapper and the signals on the Wild-One card • Copy the wrapper to your ALU library • Your ALU is already instantiated inside • Your job: • Wire up desired signals to 32 output buffers (which will be visible on the logic analyzer for testing) • Topmost buffer corresponds to LSB on LA (wire downward) • Suggestion: bring out ALUOp, 8 bits of A, B, and R, and Overflow, Zero, RST, and PCLK • One you do this, generate a netlist for the wrapper using Leonardo • Use the tutorial on the website

  6. ALU Wrapper AnalyzerData Registers from host host (out) reg Your ALU Lad bus interfacel

  7. ALU Wrapper – wildfire card Daughter card connectors Your ALU in pe0 Memory pe1 PCI interface

  8. ALU Wrapper FPGA TO PE1 Pinout wrapper ALU wrapper Daughter card connector ALU DRAM PCI host interface (LAD Bus

  9. Preparing for Synthesis • Copy the wrapper design from COElib to your project lib • Make sure that the ALU instance in the wrapper maps to your design

  10. Wrapper file

  11. Running synthesis

  12. Xilinx Synthesis setup windows

  13. Synthesisoutput

  14. Place-and-route • Once we have the netlist, we need to build the FPGA configuration file • GOAL: map netlist onto FPGA by writing to CLBs and perform routing • CLBs use registered lookup tables, so cells need to be translated into SRAM cells

  15. Place and Route Xilinx environment

  16. More setup windows

  17. Start place and route

  18. SetupPropertiesand run

  19. Convert output to bin file promgen –u 0 pe.bit –p bin -w

  20. Placing and Routing • Place and route the design… • Open a command window using Start | Run | cmd • Change to your project directory • run promgen –u 0 pe.bit –p bin -w

  21. Host interface

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