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Communicating Transaction Processes

Communicating Transaction Processes. P.S. Thiagarajan National University of Singapore Joint Work with: Abhik Roychoudhury; ……. The Main Features. To support System Level Design One Level of Abstraction higher than C, C++, VHDL .. UML-compatible MSCS + Asynchronous control flow

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Communicating Transaction Processes

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  1. Communicating Transaction Processes P.S. Thiagarajan National University of Singapore Joint Work with: Abhik Roychoudhury; …… ES Seminar

  2. The Main Features • To support System Level Design • One Level of Abstraction higher than C, C++, VHDL .. • UML-compatible • MSCS + Asynchronous control flow • Based on MSCs (Message Sequence Charts) • Sequence Diagrams ES Seminar

  3. Why System Level Design? • Closer to end-use(r) . • Less detailed and more architecture-neutral. • Easier reuse/adaptaton. • Easier to verify. • Safety-critical applications need to be correct. • Catch design errors early. • Coupling with a correct-by-construction synthesis method is an attractive option. ES Seminar

  4. What is Available? • Data flow graphs. • Automata of various kinds. • Petri nets. • State charts. • Esterel, Lustre. • SDL, UML. ES Seminar

  5. Why UML-compatible? • UML is getting rapidly established as a standard. • Mainly in software engineering projects • Increasingly so in embedded systems domain. • Offers a suite of graphical notations: • Multiple views • Behavioral and structural diagrams. • Object orientation. • Reuse, adaptation ES Seminar

  6. An Idealized Design Flow Requirements High Level Description Exec. Specifications. Intermediate representation SW/HW Implementation. ES Seminar

  7. Requirements and Exec. Specifications • Requirements : Message Sequence Charts (MSCs) • Exec. Specifications : • State charts. • UML supports both but no clear distinction made. • Other Exec. Spec. : • Petri nets, • MPAs (Message Passing Automata), …. ES Seminar

  8. MSCs • Message Sequence Charts: • Describe scenarios. • A finite pattern of interaction between agents (object instances,..). • A story ES Seminar

  9. Message Sequence Charts U1 R U2 rq rq y n ES Seminar

  10. Message Sequence Charts U1 R U2 rq rq y n ES Seminar

  11. Message Sequence Charts U1 R U2 rq rq y internal action n ES Seminar

  12. Message Sequence Charts U1 R U2 rq rq internal actions y n ES Seminar

  13. Message Sequence Charts U1 R U2 rq rq y n ES Seminar

  14. Message Sequence Charts U1 R U2 rq rq y n ES Seminar

  15. Message Sequence Charts U1 R U2 rq rq y n ES Seminar

  16. Message Sequence Charts U1 R U2 rq rq y n ES Seminar

  17. Message Sequence Charts U1 R U2 rq rq y n ES Seminar

  18. Message Sequence Charts U1 R U2 rq rq n y ES Seminar

  19. Message Sequence Charts U1 R U2 rq rq y n ES Seminar

  20. Message Sequence Charts U1 R U2 rq rq y n ES Seminar

  21. Message Sequence Charts U1 R U2 rq rq y n ES Seminar

  22. CTPs • Communicating Transaction Processes. • An executable spec. mechanism. • Based on MSCs. • A network of interacting agents. • Agent’s interaction pattern behavior: • Standard distributed system model • Interaction: • Guarded choice of MSCs. • Transaction schemes. ES Seminar

  23. Distributed System Models • Petri nets • Data flow graphs • Statecharts • Distributed transition systems (many kinds!) • Process algebras (CCS, CSP, …) ES Seminar

  24. I2 I1 PI2 PI1 IB1 IB2 B P2 ES Seminar

  25. I2 I1 PI2 PI1 IB1 IB2 B P2 ES Seminar

  26. I2 I1 PI2 PI1 IB1 IB2 B P2 ES Seminar

  27. I2 I1 PI2 PI1 IB1 IB2 B P2 ES Seminar

  28. I2 I1 PI2 PI1 IB1 IB2 B P2 ES Seminar

  29. I2 I1 PI2 PI1 IB1 IB2 B P2 But the boxes will have internal structure. A complex Transaction Scheme. ES Seminar

  30. Transaction Scheme I2 B I2 B I2 B 2data.present & B.free 2data.present & B.free  2data.present  req req y n add data waitcount2:= waitcount2 + 1 ES Seminar

  31. I2 I1 PI2 PI1 IB1 IB2 B 2data.present & B.free req y add data ES Seminar

  32. I2 I1 2data.present & B.free req PI2 y  PI1 IB1 IB2 add data B ES Seminar

  33. I2 I1 2data.present & B.free req PI2 y  PI1 IB1 IB2 add data B ES Seminar

  34. I2 I1 2data.present & B.free req PI2 y  PI1 IB1 IB2 add data B ES Seminar

  35. I2 I1 2data.present & B.free req PI2 y  PI1 IB1 IB2 add data B ES Seminar

  36. I2 I1 2data.present & B.free req PI2 y  PI1 IB1 IB2 add data B ES Seminar

  37. I2 I1 2data.present & B.free req PI2 y  PI1 IB1 IB2 add data B ES Seminar

  38. I1 P11 P11 Transaction Scheme I1 1data.present 1data.present 1data.present no-op data no-data 1data.present 1data.present 1data.present ES Seminar

  39. Determine whether a CTP is bounded. Determine if a CTP can deadlock. Determine if a CTP is well-formed. Analysis Issues ES Seminar

  40. Current Status Case Studies Modeling The CTP Model Verification Analysis SMV ES Representation Simulation; Synthesis Verilog

  41. Current Status Pankaj Jain Nikhil Jain Kamrul Hasan Talukdar Tran Tuan Anh Ge Zhiguo Case Studies Modeling The CTP Model Verification Analysis SMV ES Representation Simulation; Synthesis Verilog

  42. Future Work • Add multiple instances of a process. • Object features • Add timing constraints. • Develop the computational model. • Interactions with environment (sense, actuate) • Computational steps (control law) • Schedulability is a key issue. • HW/SW Partitioning; Architectural mapping; Synthesis? ES Seminar

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