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1 Department of Informatics, TEI of Athens, 12210 Egaleo, Athens, Greece

On the modulo 2 n +1 multiplication for diminished-1 operands C. Efstathiou 1 , I. Voyiatzis 1 , N. Sklavos 2. 1 Department of Informatics, TEI of Athens, 12210 Egaleo, Athens, Greece 2 Informatics & MM Dept, Technological Educational Institute of Patras, Greece

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1 Department of Informatics, TEI of Athens, 12210 Egaleo, Athens, Greece

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  1. On the modulo 2n+1 multiplication for diminished-1 operandsC. Efstathiou1, I. Voyiatzis1, N. Sklavos2 1 Department of Informatics, TEI of Athens, 12210 Egaleo, Athens, Greece 2 Informatics & MM Dept, Technological Educational Institute of Patras, Greece Presenter : Prof. C. Efstathiou

  2. Application of the modulo arithmetic • Correlation/convolution computation. • Cryptographic algorithms. • Design of digital signal processors (DSP) based on residue number systems (RNS), where the moduli set {2n-1, 2n, 2n+1} is extensively used. The efficient design of the modulo 2n+1 components (adders, multipliers, …) is challenging since they operate on wider (n+1)-bit operands.

  3. Existing modulo 2n+1 Multiplier Architectures • For diminished-1 operands Array Architectures: Zimmerman (1999), Wang et al [1996], Efstathiou et al [2005], Sousa and Chaves [2005] Booth Architectures: Ma [1992], Sousa and Chaves [2005] • For conventional operands Array Architectures: Hiasat [1992], Wrzyszcz and Milford [1993], Efstathiou and Vergos [2007] Booth Architectures: Sousa and Chaves [2005]

  4. Diminished-1 Representation The diminished-1 representation of binary numbers was introduced to speed up the modulo arithmetic operations. In this approach a number A is represented as while zero is handled separately. Since only n bits are required, this representation can lead to implementations with delay and area approaching that of modulo ,

  5. Proposed Architecture The proposed design is an array architecture for the modulo 2n+1 multiplication for diminished-1 operands. It is an enhancement of the design proposed at [2005] 1. In this work the introduced by the multiplication algorithm partial products are reduced from n+3 to n+1. The introduced by the reduction of the partial products matrix correction factors are merged. The derived design is more efficient compared to the previously proposed. 1"Efficient Diminished-1 Modulo 2n+1 Μultipliers", IEEE Trans. on Comp., pp. 491-496, April 2005

  6. Partial Products to be added modulo 2n+1 According to the relation which holds for the diminished-1multiplication, the partial products are

  7. Reduction of the partial product matrix (1) Introduced correction

  8. Reduction of the partial product matrix (2) The term b0 is absorbed and no correction is introduced

  9. Further reduction of the resulting partial product matrix Introduced correction : -1

  10. Resulting Partial Products

  11. Carry save addition of the partial products (1) The n partial products and the introduced correction vector are added modulo 2n+1 using a carry save adder (CSA) tree or array. According to the relation the output carries can be complemented and repositioned to the least significant bit position of the next addition introducing a correction -1 . The correction introduced by complementing and repositioning the n-1carries of the carry save addition is -(n-1)

  12. Carry save addition of the partial products (2) Let C, S the output vectors of the multi-operand addition. The sum is computed by an inverted end around carry (EAC) adder. Efficient inverted EAC parallel-prefix adder have been proposed by Zimmerman [1999], Vergos, et al [2002]. The correction introduced by these adders is -1

  13. Total correction computation The inroduced total constant correction is The least significant column of the derived partial product array has n+1 terms and one of them, let the, must be handled in the correction vector. Since the relation holds, the final correction vector is computed as

  14. Partial products of the modulo 17 multiplier

  15. Architecture of a proposed modulo 17 multiplier

  16. Comparisons The comparisons are based on the commonly used unit-gate model. In this model, the 2-input monotonic gates (NAND, AND, etc) count as one equivalent for both area and delay. The XOR, XNOR gates and the 2-to-1 multiplexer count as two equivalents. A full adder (FA) has area and delay complexity of 7 and 4 equivalents, while a half adder (HA) counts as 3 and 2 equivalents respectively. This model is realistic for the compared designs since they both have limited fanout.

  17. Comparison results 1 "Efficient Diminished-1 Modulo 2n+1 Μultipliers", IEEE Trans. on Comp., pp. 491-496, April 2005

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