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Start-Gap: Low-Overhead Near-Perfect Wear Leveling for Main Memories

Start-Gap: Low-Overhead Near-Perfect Wear Leveling for Main Memories. Moinuddin Qureshi John Karidis, Michele Franceschini Viji Srinivasan, Luis Lastras, Bulent Abali IBM T. J. Watson Research Center, Yorktown Heights, NY. 16 yrs. 4 yrs. Introduction: Lifetime Limited Memories.

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Start-Gap: Low-Overhead Near-Perfect Wear Leveling for Main Memories

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  1. Start-Gap: Low-Overhead Near-Perfect Wear Leveling for Main Memories Moinuddin QureshiJohn Karidis, Michele FranceschiniViji Srinivasan, Luis Lastras, Bulent Abali IBM T. J. Watson Research Center, Yorktown Heights, NY MICRO-2009

  2. 16 yrs 4 yrs Introduction: Lifetime Limited Memories Emerging Memory Technologies (PCM) candidate for main memory. Reasons: Scalability, Leakage Power Savings, Density, etc. Challenge : Each cell can endure 10-100 Million writes  Limited lifetime workloads With uniform write traffic, system lifetime ranges from 4-20 years

  3. Problem: Non-Uniformity in Writes Database workload (writes occur on eviction from a 256MB DRAM cache) Average Heavy non-uniformity in writes: <10% lines incur 90%+ of write traffic

  4. Baseline w/o spares Baseline (64K spare lines) Expected Lifetime with Non-Uniform Writes Num. writes before system failure x 100% Norm. Endurance = Num. writes before failure with uniform writes 20x lower Even with 64K spare lines, baseline gets 5% lifetime of ideal

  5. Outline • Problem • Background on Wear Leveling • Start Gap Wear Leveling • Randomized Start-Gap • Security Considerations • Summary

  6. Indirection Table Physical Address PCM Address Existing Proposals: Table-Based Wear Leveling Wear Leveling: Make writes uniform by remapping frequently written lines. Studied extensively for Flash Memories. Almost all proposals Table based. 

  7. Disadvantages of Table Based Methods Overheads: 1. Area of several (tens of) megabytes 2. Indirection latency (table in EDRAM/DRAM) Area overhead can be reduced with more lines per region:  Reduced effectiveness (e.g. Line0 always written)  Support for swapping large memory regions (complex) Our Goal: A wear leveling algorithm that avoids the storage, latency, and complexity of table based methods and still achieves lifetime close to ideal.

  8. Outline • Problem • Background on Wear Leveling • Start Gap Wear Leveling • Randomized Start-Gap • Security Considerations • Summary

  9. GAP  Start-Gap Wear Leveling Two registers (Start & Gap) + 1 line (GapLine) to support movement. Move GapLine every 100 writes to memory. START 0 A 1 B 2 C 3 D 4 PCMAddr = (Start+Addr); (PCMAddr >= Gap) PCMAddr++) Storage overhead: less than 8 bytes (GapLine taken from spares) Latency: Two additions (no table lookup) Write overhead: One extra write every 100 writes  1%

  10. Results for Start-Gap On average, Start-Gap gets 53% normalized endurance 10X better than baseline, but still 2x lower than Ideal. Why?

  11. Spatial Correlation in Heavily Written Regions Start-Gap moves a line to its neighbor  If heavily written regions are spatially close, Start-Gap may move hot lines to other hot lines Peaks db1 FFT Writes Localized If address space is randomized, hot regions will be spread uniformly

  12. Outline • Problem • Background on Wear Leveling • Start Gap Wear Leveling • Randomized Start-Gap • Security Considerations • Summary

  13. Static Randomizer Start-Gap Mapping Randomized Start Gap Physical Address Randomized Address PCM Address Line Addr PCM Hot lines One-to-one mapping  Invertible function. Configured at design/boot. Minor change can support Pagemode memory. Randomizer is OS unaware.

  14. Random Invertible Binary (RIB) Matrix Feistel Network (crypto) RIB Matrix b00 b01 b02 b03 b10 b11 b12 b13 b20 b21 b22 b23 b30 b31 b32 b33 a0 a1 a2 a3 x = c0 c1 c2 c3 5 byte storage (3 cycle latency) 85 byte storage (1 cycle latency) Efficient Address Space Randomization Two proposals (very little hardware)

  15. Results for Randomized Start-Gap Randomized Start-Gap achieves 97% of ideal lifetime while incurring a total storage overhead of 13 bytes.

  16. Analytical Model for Randomized Start Gap We developed a simple analytical model that uses variance in writetraffic across lines to compute norm. endurance (details in paper) Lifetime from analytical model matches very well (97% vs. 96.8%)

  17. Comparison with Table Based Methods Normalized Endurance (%) TBWL-640MB RandSGap TBWL-1.25MB Baseline 13 bytes (1 line per region) (region=128KB) Randomized Start-Gap achieves lifetime similar to hardware-intensive version of table based & avoids several tens of cycle of latency overhead

  18. Outline • Problem • Background on Wear Leveling • Start Gap Wear Leveling • Randomized Start-Gap • Security Considerations • Summary

  19. Time to 1 line failure (seconds) = Endurance* (CyclesPerWrite/CyclesPerSec) = 225 x 212 4GHz = 32 seconds Security Challenge in Lifetime Limited Memories What if an adversary knows about write endurance limit? Repeat Address Attack (RAA): repeat writes to same line. RAA can cause line failure in less than 1 minute Both baseline and randomized Start-Gap suffers from this attack. Even table based wear leveling (practical version) suffers.

  20. NumLinesInRegion < Endurance WritesPerGapMovement Security Aware Wear Leveling Solution: Divide memory into regions. One Start-Gap per region. Region size is made such that each line in region guaranteed to move once every “endurance” number of writes to region We use 256K lines per region (256 regions). Area Overhead < 1.5KB RAA now takes about 3-4 months to cause failure. With delayed writes (in paper), time to failure ranges in year(s)

  21. Outline • Problem • Background on Wear Leveling • Start Gap Wear Leveling • Randomized Start-Gap • Security Considerations • Summary

  22. Summary • Limited endurance poses lifetime and security challenge • Table based wear leveling: area and latency overhead • Start-Gap: Cost-effective wear leveling with two registers • Randomized Start-Gap: 97% of ideal endurance with 13 bytes • We took a first step towards making PCM systems secureagainst malicious attacks (RAA). Motivation for more research

  23. Advertisement HPCA 2010 Tutorial Phase Change Memory: A Systems Perspective Organizers Dr. Moinuddin K Qureshi (IBM Research) Prof. Sudhanva Gurumurthi (University Of Virginia) Dr. Bipin Rajendran (IBM Research) Date: Jan 9, 2010 (Half Day) http://www.cs.virginia.edu/~gurumurthi/PCM_tutorial/

  24. Backup Slides

  25. Supporting DRAM PageMode with Start-Gap Randomization must be done at a DRAM-Page granularity instead of line

  26. 4 months 1 week 1 minute Lifetime Under RAA attack RAA will now take about 3-4 months to cause failure. With delayed writes (in paper), time required would range in year(s).

  27. Outline • Problem • Background on Wear Leveling • Start Gap Wear Leveling • Randomized Start-Gap • Security Considerations • Summary

  28. Spare Lines

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