Digital Integrated Circuits A Design Perspective

1. Digital Integrated CircuitsA Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic ManufacturingProcess July 30, 2002

2. CMOS Process

3. A Modern CMOS Process;Think ! ; Why 1)dual well, 2)trench, 3)LDD (Lightly-Doped Drain), 4)TiSi2 ? Dual-Well Trench-Isolated CMOS Process

4. Circuit Under Design

5. Layout View;1)Why multiple contact windows? 2)Why Wp=2*Wn? 1) Current crowding Pattern size/Process Control 2) Mobility in two neighboring bands differ by about 2.5. Scalable; Scale, and process-independent precision assured Applicable to precision capacitor fabrication

6. The Manufacturing Process For a great tour through the IC manufacturing process and its different steps, check http://www.fullman.com/semiconductors/semiconductors.html Try somewhere else!

7. Photolithographic Process optical mask oxidation • Mask making by e-beam, exposure by i,g-line light source • E-beam exposure (no mask) photoresist photoresist coating removal (ashing) stepper exposure Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process spin, rinse, dry step

8. Patterning of SiO2 Chemical or plasma etch Si-substrate Hardened resist SiO 2 (a) Silicon base material Si-substrate Photoresist SiO 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 Si-substrate Hardened resist (b) After oxidation and deposition SiO of negative photoresist 2 Si-substrate UV-light Patterned (e) After etching optical mask Exposed resist SiO 2 Si-substrate Si-substrate (f) Final result after removal of resist (c) Stepper exposure

9. Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers CMOS Process at a Glance

10. p-epi (a) Base material: p+ substrate with p-epi layer + p Si N 3 4 SiO (b) After deposition of gate-oxide and 2 p-epi sacrificial nitride (acts as a buffer layer) + p (c) After plasma etch of insulating trenches using the inverse of the active area mask p + CMOS Process Walk-Through

11. SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n-well and V adjust implants Tp p (f) After p-well and V adjust implants Tn CMOS Process Walk-Through CMP: Chemical Mechanical Polish Select mask Select mask negative

12. poly(silicon) (g) After polysilicon deposition and etch n + + p (h) After n + source/drain and p + source/drain implants. These steps also dope the polysilicon. SiO 2 (i) After deposition of SiO 2 insulator and contact hole etch. CMOS Process Walk-Through LDD formation in two step implants using sidewall as the mask for the 2nd implant step; Sidewall is formed by flowing glass deposit followed by planarization.

13. Al (j) After deposition and patterning of first Al layer. Al SiO 2 (k) After deposition of SiO 2 insulator, etching of via’s, deposition and patterning of second layer of Al. CMOS Process Walk-Through

14. Advanced Metallization

15. Advanced Metallization Damascene Process; Pattern and deposit vs. conventional Deposit and pattern

16. Design Rules

17. 3D Perspective With silicon etch (trench formation) before planarization, bird’s head as well as bird’s beak is also formed. Polysilicon Aluminum Bird’s Beak*

18. Design Rules • One of the two most important interfaces (with SPICE parameter) between cell/chip layout designer and process engineer set such that density, speed and yield are maximized • Guidelines for constructing process masks • Unit dimension: Minimum line width • scalable design rules (lambda rules ; for simplicity in academia and learning purpose) • absolute dimensions (micron rules ; for production purpose)

19. Layer Color Representation Well (p,n) Yellow Active Area (n+,p+) Green Select (p+,n+) Green Polysilicon Red Metal1 Blue Metal2 Magenta Contact To Poly Black Contact To Diffusion Black Via Black CMOS Process Layers

20. Layers in 0.25 mm CMOS process

21. Intra-Layer Design Rules 4 Metal2 3

22. Transistor Layout Think what would happen if each specific rule is violated. 1.Uncontrolled W/L 2.Leaky transistor 3.Grounded drain 5.Leaky drain and Low BV of drain Bird’s Beak penetration

23. Vias and Contacts

24. Select Layer SUBSTRATE CONTACT Well contact

25. CMOS Inverter Layout

26. Layout Editor

27. Design Rule Checker (DRC) Background (on-line) mode (Max) vs. Batch mode (Cadence Dracula, Mentor Excalibur) Poly which is not over the FET active is too near from FET diffusion (Source/drain) poly_not_fet to all_diff minimum spacing = 0.14 um. Violation spot

28. V DD 3 Out In 1 GND Stick diagram of inverter Sticks Diagram • Dimensionless layout entities • Only topology is important • Final layout generated by “compaction” program Using design rule as the basis, compaction is done in horizontal followed by vertical or the other way, or some combination of these.

29. Advantages/Disadvantages of Sticks Diagram Approach vs. Polygon Layout • Adavantages • No need to worry about Design Rules • Useful for automatic cell generation including automatic pitch matching • Disadvantages • Final layout is unpredictable. • Not used for frequently used cells

30. Other tools for assuring layouts • ERC (Electrical Rule Check) • Ex. Floating node, Vdd-GND short, … • Circuit Extraction • Extract schematic from layout • Used for back-annotation of parasitic components in the post-layout simulation

31. 10/1 강의 시작

32. Packaging

33. Packaging Requirements • Electrical: Lowparasitics (L,R,C) • Mechanical: Reliable and robust • Thermal: Efficient heat removal • Economical: Cheap (package material cost, packaging yield/cost) • Protection from Radiation Damage /Cross Coupling

34. Bonding Techniques

35. Tape-Automated Bonding (TAB) Cost, Heat Removal, and Die attachment differs Depending on Ceramic or Plastic Package

36. Flip-Chip (face-down) Bonding What are pros and cons vs. face-up wire bonding?

37. Flip-chip vs. Hardware acceleration • Pros of Flip-Chip bonding; • Short distance between bonding pad and chip lead • High yield/low packaging cost • Cons • Thermal dissipation (Low power device 는 문제 없음) • Floating substrate • No way for image sensor chips.

38. Package-to-Board Interconnect

39. Package Types

40. Package Parameters

41. Multi-Chip Modules

42. Comparison between SIP and SoC • SIP(Silicon in a Package) or MCM(Multi-Chip Module); • Each chip can be fabricated in different(customized) process. • Known good die problem • Good for low/medium volume, high margin application • SoC (Systom on a Chip); • CMOS • Competitiveness comes from the optimal interconnection and integration (process, IP, design procedures, etc.) • Scale of economy market